CP2400DK Silicon Laboratories Inc, CP2400DK Datasheet - Page 38

• Manufacturer Part Number: CP2400DK
• Description: KIT EVAL SPI LCD DRIVER CP2400
• Manufacturer: Silicon Laboratories Inc

Specifications of CP2400DK

• Main Purpose: LCD Development
• Embedded: Yes
• Utilized Ic / Part: CP2400
• Primary Attributes: I²C, SMBus Interfaces
• Secondary Attributes: Up to 128 segments
• Product: Microcontroller Modules
• Core Processor: C8051F930
• Clock Speed: 20 MHz
• Interface Type: SPI
• Timers: 2
• Operating Supply Voltage: 1.8 V to 3.6 V
• Cpu Core: C8051F930
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 336-1858; 336-1858

CP2400/1/2/3
38
ULPMEM03
ULPMEM04
ULPMEM05
ULPMEM06
ULPMEM07
ULPMEM08
ULPMEM09
ULPMEM10
ULPMEM11
ULPMEM12
ULPMEM13
ULPMEM14
ULPMEM15
LCD Control Registers
LCD0CN
CONTRAST
LCD0CF
LCD0DIVL
LCD0DIVH
LCD0TOGR
LCD0PWR
Ultra Low Power Control Registers
MSCN
MSCF
ULPCN
Port I/O Configuration Registers
P0OUT
P1OUT
P2OUT
P3OUT
P4OUT
P0MDI
P1MDI
P2MDI
P3MDI
P4MDI
P0MDO
P1MDO
P2MDO
P3MDO
Register
Address
0xBC
0xBD
0x8C
0x8D
0xBA
0xBB
0x84
0x85
0x86
0x87
0x88
0x89
0x8A
0x8B
0x8E
0x8F
0x9A
0x9B
0xA0
0xA1
0xA2
0xB0
0xB1
0xB2
0xB3
0xB4
0xB5
0xB6
0xB7
0xB8
0xB9
0x90
0x95
0x96
0x97
0x98
0x99
Table 6.3. Internal Register Memory Map (Continued)
ULP Memory Byte 3
ULP Memory Byte 4
ULP Memory Byte 5
ULP Memory Byte 6
ULP Memory Byte 7
ULP Memory Byte 8
ULP Memory Byte 11
ULP Memory Byte 15
LCD0 Control
LCD0 Clock Divider High Byte
LCD0 Clock Divider Low Byte
Ultra Low Power Control
Port 1 Output Mode
Port 2 Output Mode
Port 3 Output Mode
ULP Memory Byte 9
ULP Memory Byte 10
ULP Memory Byte 12
ULP Memory Byte 13
ULP Memory Byte 14
LCD0 Contrast Adjustment
LCD0 Configuration
LCD0 Toggle Rate
LCD0 Power Mode
Master Control
Master Configuration
Port 0 Output Data Latch
Port 1 Output Data Latch
Port 2 Output Data Latch
Port 3 Output Data Latch
Port 4 Output Data Latch
Port 0 Input Mode
Port 1 Input Mode
Port 2 Input Mode
Port 3 Input Mode
Port 4 Input Mode
Port 0 Output Mode
Rev. 1.0
Description
Preserved
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
N
N
N
N
N
N
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