CP2400DK Silicon Laboratories Inc, CP2400DK Datasheet - Page 47

• Manufacturer Part Number: CP2400DK
• Description: KIT EVAL SPI LCD DRIVER CP2400
• Manufacturer: Silicon Laboratories Inc

Specifications of CP2400DK

• Main Purpose: LCD Development
• Embedded: Yes
• Utilized Ic / Part: CP2400
• Primary Attributes: I²C, SMBus Interfaces
• Secondary Attributes: Up to 128 segments
• Product: Microcontroller Modules
• Core Processor: C8051F930
• Clock Speed: 20 MHz
• Interface Type: SPI
• Timers: 2
• Operating Supply Voltage: 1.8 V to 3.6 V
• Cpu Core: C8051F930
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 336-1858; 336-1858

8.
Reset circuitry allows the CP2400/1/2/3 to be easily placed in a predefined default condition. Upon entry to this
reset state, the following events occur:





The CP2400/1/2/3 has two reset sources that place the device in the reset state. The method of entry to the reset
state determines the amount of time spent in reset. Each of the following reset sources is described in the following
sections:


Upon exit from the reset state, the device automatically starts the internal oscillator then asserts the interrupt pin.
The device is fully functional after the interrupt pin is asserted.
8.1.
After every CP2400/1/2/3 reset, the following initialization procedure is recommended to ensure proper device
operation:
All direct and indirect registers are initialized to their defined reset values.
Port I/O pins are forced into a high impedance state with a weak pull-up to V
The INT pin is forced to a logic high state.
The internal oscillator is stopped.
All interrupts (except SmaRTClock Oscillator Fail) are enabled.
Power-On
External RST Pin
Reset Sources
Reset Initialization
1. Wait for the Reset Complete Interrupt (interrupt pin assertion).
2. Disable interrupts (using INT0EN and INT1EN on page 43 and page 46) for events that will not be
3. Configure the device for the intended mode of operation.
monitored or handled by the host processor. By default, all interrupts except for SmaRTClock Oscilla-
tor Fail are enabled after every reset.
Rev. 1.0
DD
.
CP2400/1/2/3
47