CP2400DK Silicon Laboratories Inc, CP2400DK Datasheet - Page 79

• Manufacturer Part Number: CP2400DK
• Description: KIT EVAL SPI LCD DRIVER CP2400
• Manufacturer: Silicon Laboratories Inc

Specifications of CP2400DK

• Main Purpose: LCD Development
• Embedded: Yes
• Utilized Ic / Part: CP2400
• Primary Attributes: I²C, SMBus Interfaces
• Secondary Attributes: Up to 128 segments
• Product: Microcontroller Modules
• Core Processor: C8051F930
• Clock Speed: 20 MHz
• Interface Type: SPI
• Timers: 2
• Operating Supply Voltage: 1.8 V to 3.6 V
• Cpu Core: C8051F930
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 336-1858; 336-1858

Internal Register Definition 11.4. RTC0CN: SmaRTClock Control
SmaRTClock Address = 0x04
Note: The ALRM flag will remain asserted for a maximum of one SmaRTClock cycle.
Name
Reset
Bit
Type
7
6
5
4
3
2
1
0
Bit
RTC0AEN SmaRTClock Alarm Enable.
RTC0CAP SmaRTClock Timer Capture.
RTC0SET SmaRTClock Timer Set.
OSCFAIL SmaRTClock Oscillator Fail Event Flag.
MCLKEN Missing SmaRTClock Detector Enable.
RTC0EN SmaRTClock Enable.
RTC0TR SmaRTClock Timer Run Control.
Name
ALRM
RTC0EN
R/W
7
0
Enables/disables the SmaRTClock oscillator and associated bias currents.
0: SmaRTClock oscillator disabled.
1: SmaRTClock oscillator enabled.
Enables/disables the missing SmaRTClock detector.
0: Missing SmaRTClock detector disabled.
1: Missing SmaRTClock detector enabled.
Set by hardware when a missing SmaRTClock detector timeout occurs. Must be cleared by
software. The value of this bit is not defined when the SmaRTClock
oscillator is disabled.
Controls if the SmaRTClock timer is running or stopped (holds current value).
0: SmaRTClock timer is stopped.
1: SmaRTClock timer is running.
Enables/disables the SmaRTClock alarm function. Also clears the ALRM flag.
0: SmaRTClock alarm disabled.
1: SmaRTClock alarm enabled.
SmaRTClock Alarm Event
Flag and Auto Reset Enable
Reads return the state of the
alarm event flag.
Writes enable/disable the
Auto Reset function.
Writing 1 initiates a SmaRTClock timer set operation. This bit is cleared to 0 by hardware to
indicate that the timer set operation is complete.
Writing 1 initiates a SmaRTClock timer capture operation. This bit is cleared to 0 by hardware
to indicate that the timer capture operation is complete.
MCLKEN
R/W
6
0
OSCFAIL
Varies
R/W
5
Rev. 1.0
RTC0TR
R/W
Read:
0: SmaRTClock alarm event
flag is de-asserted.
1: SmaRTClock alarm event
flag is asserted.
4
0
Function
RTC0AEN
R/W
3
0
ALRM
R/W
2
0
Write:
0: Disable Auto Reset.
1: Enable Auto Reset.
CP2400/1/2/3
RTC0SET
R/W
1
0
RTC0CAP
R/W
0
0
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