CP2400DK Silicon Laboratories Inc, CP2400DK Datasheet - Page 33

• Manufacturer Part Number: CP2400DK
• Description: KIT EVAL SPI LCD DRIVER CP2400
• Manufacturer: Silicon Laboratories Inc

Specifications of CP2400DK

• Main Purpose: LCD Development
• Embedded: Yes
• Utilized Ic / Part: CP2400
• Primary Attributes: I²C, SMBus Interfaces
• Secondary Attributes: Up to 128 segments
• Product: Microcontroller Modules
• Core Processor: C8051F930
• Clock Speed: 20 MHz
• Interface Type: SPI
• Timers: 2
• Operating Supply Voltage: 1.8 V to 3.6 V
• Cpu Core: C8051F930
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 336-1858; 336-1858

SFR Definition 5.2. IOSCCN: Internal Oscillator Control
Internal Register Address = 0x33
SFR Definition 5.3. REVID: Revision Identification
Internal Register Address = 0x34
Note: To control the internal oscillator enable from an external pin (EXTCTL = 1, INTCTL = 0), first write both bits to logic 1,
Name
Reset
Name
Reset
Type
Type
7:4
Bit
7:0
Bit
Bit
Bit
3
2
1
0
then clear the INTCTL bit. See
place the device in RAM Preservation Mode. When running from an external clock, the internal oscillator may be dis-
abled by writing 0x00 to IOSCCN.
REVID[7:0] Revision ID.
Reserved Read = 0. Write = Must Write 0b.
EXTCTL
INTCTL
OSCEN
Unused
Name
Name
Varies
R/W
7
0
7
Read = 00000. Write = Don’t Care.
Oscillator Internal Control Enable.
When set to 1, forces the oscillator to remain enabled. Setting this bit to 0 will gate the clock
output, but will not disable the oscillator.
Internal Oscillator Enable.
When set to 0, disables power to the internal oscillator. When set to 1, allows the internal
oscillator to be powered (under the control of INTCTL and EXTCTL).
Oscillator External Control Enable.
When set to 1 and INTCTL is cleared to 0, a rising edge on CLK will cause the internal
oscillator to be disabled. The internal oscillator is re-enabled by the next falling edge on CLK.
Indicates the device revision. For example 0x01 indicates Revision C.
Varies
R/W
6
0
6
Section “9.2. RAM Preservation Mode” on page 50
Varies
R/W
5
0
5
Rev. 1.0
Varies
R/W
4
0
4
REVID[7:0]
R/W
Function
Function
Reserved
Varies
R/W
3
0
3
INTCTL
Varies
2
1
2
CP2400/1/2/3
for information on how to
OSCEN
Varies
R/W
1
1
1
EXTCTL
Varies
0
0
0
33