STEVAL-IFW001V1 STMicroelectronics, STEVAL-IFW001V1 Datasheet - Page 20
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STEVAL-IFW001V1
Manufacturer Part Number
STEVAL-IFW001V1
Description
BOARD EVAL BASED ON STR912FA
Manufacturer
STMicroelectronics
Datasheets
1.STEVAL-IFW001V1.pdf
(102 pages)
2.STEVAL-IFW001V1.pdf
(9 pages)
3.STEVAL-IFW001V1.pdf
(7 pages)
Specifications of STEVAL-IFW001V1
Design Resources
STEVAL-IFW001V1 Gerber Files STEVAL-IFW001V1 Schematic STEVAL-IFW001V1 Bill of Material
Main Purpose
Interface, Ethernet
Embedded
Yes, MCU, 32-Bit
Utilized Ic / Part
E-STE101P, STR912FAW44
Primary Attributes
Dual Ethernet Transceivers for Full Duplex Communication
Secondary Attributes
Up to 32 MII Addresses, UART, I2C, SPI, with RJ45 Connectors
Silicon Manufacturer
ST Micro
Core Architecture
ARM
Core Sub-architecture
ARM9
Silicon Core Number
STR9
Silicon Family Name
STR91x
For Use With
497-8263 - BOARD EXTENSION STEVAL-IFW001V1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-8262
Functional overview
Table 6.
3.10
3.10.1
20/102
31 (low priority)
IRQ channel
hardware
priority
25
26
27
28
29
30
VIC IRQ channels (continued)
Clock control unit (CCU)
The CCU generates a master clock of frequency f
also generates individually scaled and gated clock sources to each of the following
functional blocks within the STR91xFA.
●
●
●
●
●
●
●
Master clock sources
The master clock in the CCU (f
firmware control, the CPU can switch between the three CCU inputs without introducing any
glitches on the master clock output. Inputs to the CCU are:
●
●
●
VIC input
channel
VIC1.10
VIC1.11
VIC1.12
VIC1.13
VIC1.14
VIC1.15
CPU, f
Advanced High-performance Bus (AHB), f
Advanced Peripheral Bus (APB), f
Flash Memory Interface (FMI), f
External Memory Interface (EMI), f
UART Baud Rate Generators, f
USB, f
Main Oscillator (f
crystal connected to STR91xFA pins X1_CPU and X2_CPU, or an external oscillator
device connected to pin X1_CPU.
PLL (f
master clock output up to 96 MHz (programmable). By default, at power-up the master
clock is sourced from the main oscillator until the PLL is ready (locked) and then the
CPU may switch to the PLL source under firmware control. The CPU can switch back to
the main oscillator source at any time and turn off the PLL for low-power operation. The
PLL is always turned off in Sleep mode.
RTC (f
X2_RTC, or an external oscillator connected to pin X1_RTC to constantly run the real-
time clock unit. This 32.768 kHz clock source can also be used as an input to the CCU
to run the CPU in slow clock mode for reduced power.
VIC1.9
PLL
USB
CPUCLK
RTC
). The PLL takes the 4 to 25 MHz oscillator clock as input and generates a
Wake-up Group 0
Wake-up Group 1
Wake-up Group 2
Wake-up Group 3
). A 32.768 kHz external crystal can be connected to pins X1_RTC and
Wake-Up (all)
Logic block
PFQ-BC
USB
OSC
). The source for the main oscillator input is a 4 to 25 MHz external
MSTR
Doc ID 13495 Rev 6
Logic OR of 8 interrupt sources: RTC, USB Resume, pins P3.2 to
Special use of interrupts from Prefetch Queue and Branch Cache
Logic OR of all 32 inputs of Wake-Up unit (30 pins, RTC, and
) is derived from one of three clock input sources. Under
BAUD
FMICLK
USB Bus Resume Wake-up (also input to wake-up unit)
PCLK
BCLK
Logic OR of 8 interrupts from pins P5.0 to P5.7
Logic OR of 8 interrupts from pins P6.0 to P6.7
Logic OR of 8 interrupts from pins P7.0 to P7.7
HCLK
MSTR
Interrupt source
. From this master clock the CCU
USB Resume)
P3.7
STR91xFAxxx