STEVAL-IFW001V1 STMicroelectronics, STEVAL-IFW001V1 Datasheet - Page 34

• Manufacturer Part Number: STEVAL-IFW001V1
• Description: BOARD EVAL BASED ON STR912FA
• Manufacturer: STMicroelectronics

Specifications of STEVAL-IFW001V1

• Design Resources: STEVAL-IFW001V1 Gerber Files STEVAL-IFW001V1 Schematic STEVAL-IFW001V1 Bill of Material
• Main Purpose: Interface, Ethernet
• Embedded: Yes, MCU, 32-Bit
• Utilized Ic / Part: E-STE101P, STR912FAW44
• Primary Attributes: Dual Ethernet Transceivers for Full Duplex Communication
• Secondary Attributes: Up to 32 MII Addresses, UART, I2C, SPI, with RJ45 Connectors
• Silicon Manufacturer: ST Micro
• Core Architecture: ARM
• Core Sub-architecture: ARM9
• Silicon Core Number: STR9
• Silicon Family Name: STR91x
• For Use With: 497-8263 - BOARD EXTENSION STEVAL-IFW001V1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8262

Functional overview
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A single device can play the role of Master or Slave, or a single device can be a Slave only.
A Master or Slave device has the ability to suspend data transfers if the device needs more
time to transmit or receive data.
Each I2C interface on the STR91xFA has the following features:
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SSP interfaces (SPI, SSI, and MICROWIRE) with DMA
The STR91xFA supports two independent Synchronous Serial Port (SSP) interfaces,
designated SSP0, and SSP1. Primary use of each interface is for supporting the industry
standard Serial Peripheral Interface (SPI) protocol, but also supporting the similar
Synchronous Serial Interface (SSI) and MICROWIRE communication protocols.
SPI is a three or four wire synchronous serial communication channel, capable of full-duplex
operation. In three-wire configuration, there is a clock signal, and two data signals (one data
signal from Master to Slave, the other from Slave to Master). In four-wire configuration, an
additional Slave Select signal is output from Master and received by Slave.
The SPI clock signal is a gated clock generated from the Master and regulates the flow of
data bits. The Master may transmit at a variety of baud rates, up to 24 MHz
In multi-Slave operation, no more than one Slave device can transmit data at any given time.
Slave selection is accomplished when a Slave’s “Slave Select” input is permanently
grounded or asserted active-low by a Master device. Slave devices that are not selected do
not interfere with SPI activities. Slave devices ignore the clock signals and keep their data
output pins in high-impedance state when not selected. The STR91xFA supports SPI multi-
Master operation because it provides collision detection.
Each SSP interface on the STR91xFA has the following features:
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Programmable clock supports various rates up to I2C Standard rate (100 KHz) or Fast
rate (400 KHz).
Serial I/O Engine (SIOE) takes care of serial/parallel conversion; bus arbitration; clock
generation and synchronization; and handshaking
Multi-master capability
7-bit or 10-bit addressing
Full-duplex, three or four-wire synchronous transfers
Master or Slave operation
Programmable clock bit rate with prescaler, up to 24 MHz for Master mode and 4 MHz
for Slave mode
Separate transmit and receive FIFOs, each 16-bits wide and 8 locations deep
Programmable data frame size from 4 to 16 bits
Programmable clock and phase polarity
Specifically for MICROWIRE protocol:
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Specifically for SSI protocol:
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Half-duplex transfers using 8-bit control message
Full-duplex four-wire synchronous transfer
Transmit data pin tri-stateable when not transmitting
Doc ID 13495 Rev 6
STR91xFAxxx