STEVAL-IFW001V1 STMicroelectronics, STEVAL-IFW001V1 Datasheet - Page 48

• Manufacturer Part Number: STEVAL-IFW001V1
• Description: BOARD EVAL BASED ON STR912FA
• Manufacturer: STMicroelectronics

Specifications of STEVAL-IFW001V1

• Design Resources: STEVAL-IFW001V1 Gerber Files STEVAL-IFW001V1 Schematic STEVAL-IFW001V1 Bill of Material
• Main Purpose: Interface, Ethernet
• Embedded: Yes, MCU, 32-Bit
• Utilized Ic / Part: E-STE101P, STR912FAW44
• Primary Attributes: Dual Ethernet Transceivers for Full Duplex Communication
• Secondary Attributes: Up to 32 MII Addresses, UART, I2C, SPI, with RJ45 Connectors
• Silicon Manufacturer: ST Micro
• Core Architecture: ARM
• Core Sub-architecture: ARM9
• Silicon Core Number: STR9
• Silicon Family Name: STR91x
• For Use With: 497-8263 - BOARD EXTENSION STEVAL-IFW001V1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8262

Pin description
Table 8.
48/102
32
33
34
37
38
39
40
41
42
43
80
79
78
77
12
4
3
2
1
9
Package
128
127
126
125
124
53
54
55
59
60
61
63
65
66
68
12
18
3
2
1
M10
M11
M12
K11
L10
G6
K7
C2
B2
A1
B3
C4
B4
A4
D5
E4
F6
L7
J8
L9
Device pin description (continued)
USBCLK
name
_P2.7
P2.6
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
P5.0
P5.1
Pin
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/0
I/0
Default pin
GP Input, HiZ
GP Input, HiZ
GP Input, HiZ
GP Input, HiZ
GP Input, HiZ
GP Input, HiZ
GP Input, HiZ
GP Input, HiZ
GP Input, HiZ
GP Input, HiZ
GP Input, HiZ
GP Input, HiZ
GP Input, HiZ
GP Input, HiZ
GP Input, HiZ
GP Input, HiZ
GP Input, HiZ
GP Input, HiZ
GP Input, HiZ
GP Input, HiZ
function
GPIO_2.6,
GPIO_2.7,
GPIO_3.0,
GPIO_3.1,
GPIO_3.2,
GPIO_3.3,
GPIO_3.4,
GPIO_3.5,
GPIO_3.6,
GPIO_3.7,
GPIO_4.0,
GPIO_4.1,
GPIO_4.2,
GPIO_4.3,
GPIO_4.4,
GPIO_4.5,
GPIO_4.6,
GPIO_4.7,
GPIO_5.0,
GPIO_5.1,
/ADC Ext. trigger
Ext DMA requst
Ext DMA requst
USB_CLK48M,
48MHz to USB
ADC input chnl
ADC input chnl
ADC input chnl
ADC input chnl
ADC input chnl
ADC input chnl
ADC input chnl
ADC input chnl
DMA_RQST0,
DMA_RQST1,
External Intr
External Intr
External Intr
External Intr
External Intr
External Intr
External Intr
External Intr
function
Default
EXINT2,
EXINT3,
EXINT4,
EXINT5,
EXINT6,
EXINT7,
EXINT8,
EXINT9,
input
ADC0,
ADC1,
ADC2,
ADC3,
ADC4,
ADC5,
ADC6,
ADC7,
-
Doc ID 13495 Rev 6
SSP mstr data in
SSP mstr data in
SSP slv select in
UART rcv data
UART rcv data
UART rcv data
UART rcv data
SSP slv dat in
SSP slv sel in
CAN rcv data
SSP1_SCLK,
SSP slv clk in
SSP1_MOSI,
TIM0_ICAP1,
Input Capture
TIM0_ICAP2,
Input Capture
TIM1_ICAP1,
Input Capture
TIM1_ICAP2,
Input Capture
TIM2_ICAP1,
Input Capture
TIM2_ICAP2,
Input Capture
TIM3_ICAP1,
Input Capture
TIM3_ICAP2,
Input Capture
CAN rcv data
SSP0_MISO,
UART0_RxD,
UART2_RxD,
UART1_RxD,
SSP1_MISO,
UART0_RxD,
Alternate
SSP0_NSS,
SSP1_NSS,
CAN_RX,
CAN_RX,
input 1
Alternate
output 1
GPIO_2.6,
GP Output
GPIO_2.7,
GP Output
GPIO_3.0,
GP Output
GPIO_3.1,
GP Output
GPIO_3.2,
GP Output
GPIO_3.3,
GP Output
GPIO_3.4,
GP Output
GPIO_3.5,
GP Output
GPIO_3.6,
GP Output
GPIO_3.7,
GP Output
GPIO_4.0,
GP Output
GPIO_4.1,
GP Output
GPIO_4.2,
GP Output
GPIO_4.3,
GP Output
GPIO_4.4,
GP Output
GPIO_4.5,
GP Output
GPIO_4.6,
GP Output
GPIO_4.7,
GP Output
GPIO_5.0,
GP Output
GPIO_5.1,
GP Output
Alternate functions
SSP mstr dat out
SSP slv data out
SSP mstr sel out
SSP mstr clk out
SSP slv data out
SSP mstr sel out
Out comp/PWM
Out comp/PWM
Out comp/PWM
Out comp/PWM
ETM trace clock
UART xmit data
UART xmit data
UART xmit data
TIM0_OCMP1,
TIM0_OCMP2,
TIM1_OCMP1,
TIM1_OCMP2,
TIM2_OCMP1,
TIM2_OCMP2,
TIM3_OCMP1,
TIM3_OCMP2,
ETM_TRCLK,
SSP1_SCLK,
SSP0_MISO,
SSP1_MISO,
SSP1_MOSI,
CAN Tx data
CAN Tx data
Alternate
SSP0_NSS,
SSP1_NSS,
UART2_TX,
UART0_TX,
UART1_TX,
output 2
Out comp
Out comp
Out comp
Out comp
CAN_TX,
CAN_TX,
STR91xFAxxx
ETM pipe status
ETM pipe status
ETM pipe status
ETM pipe status
ETM_TRSYNC,
Out comp/PWM
Out comp/PWM
UART xmit data
UART xmit data
Out comp/PWM
ETM_TRSYNC,
UART xmit data
UART xmit data
ETM trace sync
Data Trmnl Rdy
Ready To Send
ETM trace sync
TIM0_OCMP1,
TIM1_OCMP1,
TIM1_OCMP1,
ETM_PSTAT2,
ETM_PSTAT0,
ETM_PSTAT1,
ETM_PSTAT2,
UART0_DTR,
UART0_RTS,
CAN Tx data
Alternate
ETM_PCK0,
ETM_PCK1,
ETM_PCK2,
ETM_PCK3,
UART0_TX,
UART2_TX,
ETM Packet
ETM Packet
ETM Packet
ETM Packet
UART0_TX,
UART2_TX,
output 3
CAN_TX,