STEVAL-IFW001V1 STMicroelectronics, STEVAL-IFW001V1 Datasheet - Page 46
![BOARD EVAL BASED ON STR912FA](/photos/9/9/90953/steval-ifw001v1_sml.jpg)
STEVAL-IFW001V1
Manufacturer Part Number
STEVAL-IFW001V1
Description
BOARD EVAL BASED ON STR912FA
Manufacturer
STMicroelectronics
Datasheets
1.STEVAL-IFW001V1.pdf
(102 pages)
2.STEVAL-IFW001V1.pdf
(9 pages)
3.STEVAL-IFW001V1.pdf
(7 pages)
Specifications of STEVAL-IFW001V1
Design Resources
STEVAL-IFW001V1 Gerber Files STEVAL-IFW001V1 Schematic STEVAL-IFW001V1 Bill of Material
Main Purpose
Interface, Ethernet
Embedded
Yes, MCU, 32-Bit
Utilized Ic / Part
E-STE101P, STR912FAW44
Primary Attributes
Dual Ethernet Transceivers for Full Duplex Communication
Secondary Attributes
Up to 32 MII Addresses, UART, I2C, SPI, with RJ45 Connectors
Silicon Manufacturer
ST Micro
Core Architecture
ARM
Core Sub-architecture
ARM9
Silicon Core Number
STR9
Silicon Family Name
STR91x
For Use With
497-8263 - BOARD EXTENSION STEVAL-IFW001V1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-8262
Pin description
5.2
5.2.1
46/102
1
2
3
4
5
6
7
8
9
Default pin functions
During and just after reset, all pins on ports 0-9 default to high-impedance input mode until
CPU firmware assigns other functions to the pins. This initial input mode routes all pins on
ports 0-9 to be read as GPIO inputs as shown in the “Default Pin Function” column of
Table
shown in the “Default Input Function” column of
remain until CPU firmware makes other assignments. At any time, even after the CPU
assigns pins to alternate functions, the CPU may always read the state of any pin on ports
0-9 as a GPIO input. CPU firmware may assign alternate functions to port pins as shown in
columns “Alternate Input 1” or “Alternate Output 1, 2, 3” of
registers at run-time.
General notes on pin usage
Since there are no internal or programmable pull-up resistors on ports 0-9, it is advised to
pull down to ground, or pull up to VDDQ (using max. 47 K Ω resistors), all unused pins on
port 0-9. Another solution is to use the GPIO control registers to configure the unused pins
on ports 0-9 as output low level. The purpose of this is to reduce noise susceptibility, noise
generation, and minimize power consumption
All pins on ports 0 - 9 are 5V tolerant
Pins on ports 0,1,2,4,5,7,8,9 have 4 mA drive and 4mA sink. Ports 3 and 6 have 8 mA drive
and 8 mA sink.
For 8-bit non-muxed EMI operation: Port 8 is eight bits of data, ports 7 and 9 are 16 bits of
address.
For 16-bit muxed EMI operation: Ports 8 and 9 are 16 bits of muxed address and data bits,
port 7 is up to eight additional bits of high-order address
Signal polarity is programmable for interrupt request inputs, EMI_ALE, timer input capture
inputs and output compare/PWM outputs, motor control tach and emergency stop inputs,
and motor control phase outputs.
HiZ = High Impedance, V = Voltage Source, G = Ground, I/O = Input/Output
STR910FA devices do not support USB. On these devices USBDP and USBDN signals are
"Not Used" (USBDN is not connected, USBDP must be pulled up by a 1.5K ohm resistor to
VDDQ), and all functions named “USB" are not available.
STR910FA 128-pin and 144-ball devices do not support Ethernet. On these devices
PHYCLK and all functions named “MII*" are not available.
8. Simultaneously, certain port pin signals are also routed to other functional inputs as
Doc ID 13495 Rev 6
Table
8, and these pin input functions will
Table 8
by writing to control
STR91xFAxxx