STEVAL-IFW001V1 STMicroelectronics, STEVAL-IFW001V1 Datasheet - Page 88
![BOARD EVAL BASED ON STR912FA](/photos/9/9/90953/steval-ifw001v1_sml.jpg)
STEVAL-IFW001V1
Manufacturer Part Number
STEVAL-IFW001V1
Description
BOARD EVAL BASED ON STR912FA
Manufacturer
STMicroelectronics
Datasheets
1.STEVAL-IFW001V1.pdf
(102 pages)
2.STEVAL-IFW001V1.pdf
(9 pages)
3.STEVAL-IFW001V1.pdf
(7 pages)
Specifications of STEVAL-IFW001V1
Design Resources
STEVAL-IFW001V1 Gerber Files STEVAL-IFW001V1 Schematic STEVAL-IFW001V1 Bill of Material
Main Purpose
Interface, Ethernet
Embedded
Yes, MCU, 32-Bit
Utilized Ic / Part
E-STE101P, STR912FAW44
Primary Attributes
Dual Ethernet Transceivers for Full Duplex Communication
Secondary Attributes
Up to 32 MII Addresses, UART, I2C, SPI, with RJ45 Connectors
Silicon Manufacturer
ST Micro
Core Architecture
ARM
Core Sub-architecture
ARM9
Silicon Core Number
STR9
Silicon Family Name
STR91x
For Use With
497-8263 - BOARD EXTENSION STEVAL-IFW001V1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-8262
- Current page: 88 of 102
- Download datasheet (3Mb)
Electrical characteristics
7.12.5
88/102
SPI electrical characteristics
V
Table 46.
Figure 30. SPI slave timing diagram with CPHA = 0
MISO
MOSI
DDQ
1/t
t
t
Symbol
w(SCLKH)
w(SCLKL)
t
t
t
t
r(SCLK)
f(SCLK)
t
t
t
t
dis(SO)
t
t
f
t
t
su(SS)
t
su(MI)
t
v(MO)
h(MO)
NSS
SCLK
c(SCLK)
su(SI)
a(SO)
v(SO)
h(SO)
h(SS)
h(MI)
h(SI)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
OUTPUT
INPUT
= 2.7 - 3.6 V, V
INPUT
SPI clock frequency
SPI clock rise and fall times 50pF load
SS setup time
SS hold time
SCLK high and low time
Data input setup time
Data input hold time
Data output access time
Data output disable time
Data output valid time
Data output hold time
Data output valid time
Data output hold time
SPI electrical characteristics
t
a(SO)
t
su(NSS)
t
su(SI)
Parameter
DD
= 1.65 - 2 V, T
t
t
MSB IN
w(SCLKH)
w(SCLKL)
MSB OUT
Doc ID 13495 Rev 6
t
t
h(SI)
c(SCLK)
A
t
Master
Slave
Slave
Slave
Master
Slave
Master
Slave
Master
Slave
Slave
Slave
Slave (after enable
edge)
Master (before capture
edge)
v(SO)
= -40 / 85 °C unless otherwise specified.
Test conditions
BIT6 OUT
BIT1 IN
t
h(SO)
t
t
r(SCLK)
f(SCLK)
TBD
TBD
0.25
0.25
Typ
1
1
1
5
6
0
LSB IN
Value
0.1
LSB OUT
t
h(NSS)
Max
24
STR91xFAxxx
6
4
6
6
t
V/ns
dis(SO)
t
MHz
Unit
PCLK
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