STEVAL-IFW001V1 STMicroelectronics, STEVAL-IFW001V1 Datasheet - Page 63
![BOARD EVAL BASED ON STR912FA](/photos/9/9/90953/steval-ifw001v1_sml.jpg)
STEVAL-IFW001V1
Manufacturer Part Number
STEVAL-IFW001V1
Description
BOARD EVAL BASED ON STR912FA
Manufacturer
STMicroelectronics
Datasheets
1.STEVAL-IFW001V1.pdf
(102 pages)
2.STEVAL-IFW001V1.pdf
(9 pages)
3.STEVAL-IFW001V1.pdf
(7 pages)
Specifications of STEVAL-IFW001V1
Design Resources
STEVAL-IFW001V1 Gerber Files STEVAL-IFW001V1 Schematic STEVAL-IFW001V1 Bill of Material
Main Purpose
Interface, Ethernet
Embedded
Yes, MCU, 32-Bit
Utilized Ic / Part
E-STE101P, STR912FAW44
Primary Attributes
Dual Ethernet Transceivers for Full Duplex Communication
Secondary Attributes
Up to 32 MII Addresses, UART, I2C, SPI, with RJ45 Connectors
Silicon Manufacturer
ST Micro
Core Architecture
ARM
Core Sub-architecture
ARM9
Silicon Core Number
STR9
Silicon Family Name
STR91x
For Use With
497-8263 - BOARD EXTENSION STEVAL-IFW001V1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-8262
- Current page: 63 of 102
- Download datasheet (3Mb)
STR91xFAxxx
7.5.1
LVD delay timing
Case 1: When V
(introduced by the VDD rising edge), a new ~10 ms delay starts before the release of
RESET_OUTn. See
Figure 12. LVD reset delay case 1
Case 2: When V
(introduced by the VDD rising edge), RESET_OUTn will be released immediately at the end
of the delay. No new delay is introduced in this case. See
Figure 13. LVD reset delay case 2
Case 3: When V
RESET_OUTn will be released at the end of a ~10 ms delay. See
Figure 14. LVD reset delay case 3
V
V
RESET_OUTn (blue)
V
V
V
V
RESET_OUTn (blue)
RESET_OUTn (blue)
DD
DDQ
DD
DDQ
DD
DDQ
(green)
(green)
(green)
(red)
(red)
(red)
V
DDQ
DDQ
DD
V
DD_LVD+
DD_LVD+
reaches the V
Figure 12.
reaches the V
reaches the V
V
V
~10 ms delay
DDQ_LVD+
DDQ_LVD+
~10 ms delay
Doc ID 13495 Rev 6
DD_LVD+
DDQ_LVD+
DDQ_LVD+
V
DD_LVD+
threshold after the V
threshold after the first ~10 ms delay
threshold before the first ~10 ms delay
~10 ms delay
Figure 13.
V
DDQ_LVD+
DDQ
Electrical characteristics
Figure 14
rising edge,
~10 ms delay
63/102
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