OM11014 NXP Semiconductors, OM11014 Datasheet - Page 45

• Manufacturer Part Number: OM11014
• Description: BOARD EVAL FOR LPC2919
• Manufacturer: NXP Semiconductors
• Series: Keilr
• Type: MCUr

Specifications of OM11014

• Contents: Board, Cable, CD
• For Use With/related Products: LPC2919
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• Other names: 568-4360

NXP Semiconductors
LPC2917_19_1
Product data sheet
8.8.4.4 CGU pin description
8.8.5.1 Overview
8.8.5.2 Description
8.8.5 Reset Generation Unit (RGU)
Triple output phases:
clock outputs can be enabled by setting register P23EN to logic 1, thus giving three clocks
with a 120 phase difference. In this mode all three clocks generated by the analog
section are sent to the output dividers. When the PLL has not yet achieved lock the
second and third phase output dividers run unsynchronized, which means that the phase
relation of the output clocks is unknown. When the PLL LOCK register is set the second
and third phase of the output dividers are synchronized to the main output clock CLKOUT
PLL, thus giving three clocks with a 120 phase difference.
Direct output mode:
clock is divided by 2, 4, 8 or 16 depending on the value on the PSEL[1:0] input, giving an
output clock with a 50 % duty cycle. If a higher output frequency is needed the CCO clock
can be sent directly to the output by setting DIRECT to logic 1. Since the CCO does not
directly generate a 50 % duty cycle clock, the output clock duty cycle in this mode can
deviate from 50 %.
Power-down control:
consumption when the PLL clock is not needed. This is enabled by setting the PD control
register bit. In this mode the analog section of the PLL is turned off, the oscillator and the
phase-frequency detector are stopped and the dividers enter a reset state. While in
Power-down mode the LOCK output is low, indicating that the PLL is not in lock. When
Power-down mode is terminated by clearing the PD control-register bit the PLL resumes
normal operation, and makes the LOCK signal high once it has regained lock on the input
clock.
The CGU module in the LPC2917/19 has the pins listed in
Table 24.
The key features of the Reset Generation Unit (RGU) are:
The RGU controls all internal resets.
Each reset output is defined as a (combination of) reset input sources including the
external reset input pins and internal power-on reset, see
listed in this table form a sort of cascade to provide the multiple levels of impact that a
reset may have. The combined input sources are logically OR-ed together so that
activating any of the listed reset sources causes the output to go active.
Symbol
XOUT_OSC
XIN_OSC
•
•
•
•
Reset controlled individually per subsystem
Automatic reset stretching and release
Monitor function to trace resets back to source
Register write-protection mechanism to prevent unintentional resets
CGU pins
In normal operating mode (with DIRECT set to logic 0) the CCO
Direction
OUT
IN
A Power-down mode has been incorporated to reduce power
For applications that require multiple clock phases two additional
Rev. 01 — 31 July 2008
Description
oscillator crystal output
oscillator crystal input or external clock input
ARM9 microcontroller with CAN and LIN
Table
Table 24
25. The first five resets
LPC2917/19
below.
© NXP B.V. 2008. All rights reserved.
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