C8051F040-TB Silicon Laboratories Inc, C8051F040-TB Datasheet - Page 165

• Manufacturer Part Number: C8051F040-TB
• Description: BOARD PROTOTYPING W/C8051F040
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F040-TB

• Contents: Board
• Processor To Be Evaluated: C8051F04x
• Interface Type: USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F040
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

13. Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this
reset state, the following occur:
•
•
•
•
All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal
data memory are unaffected during a reset; any previously stored data is preserved. However, since the
stack pointer SFR is reset, the stack is effectively lost even though the data on the stack are not altered.
The I/O port latches are reset to 0xFF (all logic 1s), activating internal weak pullups which take the external
I/O pins to a high state. For V
timeout.
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the inter-
nal oscillator running at its lowest frequency. Refer to Section
tion on selecting and configuring the system clock source. The Watchdog Timer is enabled using its
longest timeout interval (see Section
source is stable, program execution begins at location 0x0000.
There are seven sources for putting the MCU into the reset state: power-on, power-fail, external /RST pin,
external CNVSTR0 signal, software command, Comparator0, Missing Clock Detector, and Watchdog
Timer. Each reset source is described in the following sections.
CIP-51 halts program execution
Special Function Registers (SFRs) are initialized to their defined reset values
External port pins are forced to a known state
Interrupts and timers are disabled.
(Port I/O)
XTAL1
XTAL2
CP0+
CP0-
Generator
Internal
Clock
Crossbar
OSC
Comparator0
CNVSTR
DD
+
-
(CNVSTR
enable)
reset
Monitor resets, the /RST pin is driven low until the end of the V
enable)
Figure 13.1. Reset Sources
(CP0
reset
Clock Select
System
Clock
“13.7. Watchdog Timer
Detector
Missing
Clock
(one-
shot)
Microcontroller
EN
Extended Interrupt
Rev. 1.5
CIP-51
Handler
V
Core
DD
EN
WDT
C8051F040/1/2/3/4/5/6/7
PRE
Supply
Monitor
+
-
Software Reset
System Reset
Reset” on page 167). Once the system clock
“14.
VDD Monitor
reset enable
Timeout
Supply
Reset
Oscillators” on page
(wired-OR)
(wired-OR)
Reset
Funnel
173
RST
for informa-
DD
reset
165