C8051F040-TB Silicon Laboratories Inc, C8051F040-TB Datasheet - Page 272

BOARD PROTOTYPING W/C8051F040

C8051F040-TB

Manufacturer Part Number
C8051F040-TB
Description
BOARD PROTOTYPING W/C8051F040
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheets

Specifications of C8051F040-TB

Contents
Board
Processor To Be Evaluated
C8051F04x
Interface Type
USB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F040
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
C8051F040/1/2/3/4/5/6/7
21.5. Frame and Transmission Error Detection
All Modes:
The Transmit Collision bit (TXCOL0 bit in register SSTA0) reads '1' if user software writes data to the
SBUF0 register while a transmit is in progress.
Modes 1, 2, and 3:
The Receive Overrun bit (RXOV0 in register SSTA0) reads '1' if a new data byte is latched into the receive
buffer before software has read the previous byte. The Frame Error bit (FE0 in register SSTA0) reads '1' if
an invalid (low) STOP bit is detected.
272
RX
Master
Device
Figure 21.7. UART Multi-Processor Mode Interconnect Diagram
TX
RX
Device
Slave
TX
Rev. 1.5
RX
Device
Slave
TX
RX
Device
Slave
TX
+5V

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