C8051F040-TB Silicon Laboratories Inc, C8051F040-TB Datasheet - Page 315

• Manufacturer Part Number: C8051F040-TB
• Description: BOARD PROTOTYPING W/C8051F040
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F040-TB

• Contents: Board
• Processor To Be Evaluated: C8051F04x
• Interface Type: USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F040
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Bit7:
Bits6-4:
Bits3-1:
Bit0:
CIDL
R/W
Bit7
CIDL: PCA0 Counter/Timer Idle Control.
Specifies PCA0 behavior when CPU is in Idle Mode.
0: PCA0 continues to function normally while the system controller is in Idle Mode.
1: PCA0 operation is suspended while the system controller is in Idle Mode.
UNUSED. Read = 000b, Write = don't care.
CPS2-CPS0: PCA0 Counter/Timer Pulse Select.
These bits select the timebase source for the PCA0 counter
ECF: PCA Counter/Timer Overflow Interrupt Enable.
This bit sets the masking of the PCA0 Counter/Timer Overflow (CF) interrupt.
0: Disable the CF interrupt.
1: Enable a PCA0 Counter/Timer Overflow interrupt request when CF (PCA0CN.7) is set.
Notes:
CPS2
1. The minimum high or low time for the ECI input signal is at least 2 system clock cycles.
2. External oscillator source divided by 8 is synchronized with the system clock.
0
0
0
0
1
1
1
1
R/W
Bit6
—
CPS1
SFR Definition 24.2. PCA0MD: PCA0 Mode
0
0
1
1
0
0
1
1
R/W
Bit5
—
CPS0
0
1
0
1
0
1
0
1
R/W
Bit4
—
System clock divided by 12
System clock divided by 4
Timer 0 overflow
High-to-low transitions on ECI
divided by 4)
System clock
External clock divided by 8
Reserved
Reserved
Rev. 1.5
CPS2
R/W
Bit3
C8051F040/1/2/3/4/5/6/7
CPS1
R/W
Bit2
Timebase
2
CPS0
1
R/W
Bit1
(max rate = system clock
SFR Address:
SFR Page:
ECF
R/W
Bit0
0xD9
0
00000000
Reset Value
313