C8051F040-TB Silicon Laboratories Inc, C8051F040-TB Datasheet - Page 208

• Manufacturer Part Number: C8051F040-TB
• Description: BOARD PROTOTYPING W/C8051F040
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F040-TB

• Contents: Board
• Processor To Be Evaluated: C8051F04x
• Interface Type: USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F040
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

C8051F040/1/2/3/4/5/6/7
17.1.6. External Memory Interface Pin Assignments
If the External Memory Interface (EMIF) is enabled on the Low ports (Ports 0 through 3), EMIFLE (XBR2.5)
should be set to a logic 1 so that the Crossbar will not assign peripherals to P0.7 (/WR), P0.6 (/RD), and, if
the External Memory Interface is in Multiplexed mode, P0.5 (ALE). Figure 17.4 shows an example Cross-
bar Decode Table with EMIFLE=1 and the EMIF in Multiplexed mode. Figure 17.5 shows an example
Crossbar Decode Table with EMIFLE=1 and the EMIF in Non-multiplexed mode.
If the External Memory Interface is enabled on the Low ports and an off-chip MOVX operation occurs, the
External Memory Interface will control the output states (logic 1 or logic 0) of the affected Port pins during
the execution phase of the MOVX instruction, regardless of the settings of the Crossbar registers or the
Port Data registers. The output configuration (push-pull or open-drain) of the Port pins is not affected by
the EMIF operation, except that Read operations will explicitly disable the output drivers on the Data Bus.
In most cases, GPIO pins used in EMIF operations (especially the /WR and /RD lines) should be
configured as push-pull and ‘parked’ at a logic 1 state. See
Interface and On-Chip XRAM” on page 187
208
TX0
RX0
SCK
MISO
MOSI
NSS
SDA
SCL
TX1
RX1
CEX0
CEX1
CEX2
CEX3
CEX4
CEX5
ECI
CP0
CP1
CP2
T0
/INT0
T1
/INT1
T2
T2EX
T3
T3EX
T4
T4EX
/SYSCLK
CNVSTR0
CNVSTR2
PIN I/O 0
z
z
z
z
z
z z z z z
z z z z z
z z z z z
z z z z z
z z z z z
z z z z z
z z z z z
z z z z z
z z z z z
z z z z z
z z z z z
z z z z z
z z z z z
z z z z z
z z z z z
z z z z z
z z z z z
z
z
z
z
z
1
z
z
z z z
z z z
z z z
z
2
z
z
z z
z z
z z
z
(EMIFLE = 1; EMIF in Multiplexed Mode; P1MDIN = 0xFF)
3
P0
z
z
z
4
5
6
Figure 17.4. Priority Crossbar Decode Table
7
z
z z
z z z
z z z z
z z z z z
z z z z z z
z z z z z z z
z z z z z z z z
z z z z z z z z
z
z z z z z z z z
z z z z z z z z
z z z z z z z z
z z z z z z z z
z z z z z z z z
z z z z z z z z
z z z z z z z z
z z z z z z z z
z z z z z z z z
z z z z z z z z
z z z z z z z z
z z z z z z z z
z z z z z z z z
z z z z z z z z
z z z z z z z z
z z z z z z z z
z z z z z z z z
0
AIN1 Inputs/Non-muxed Addr H
z z z z z z z
1
z z z z z z
2
NSS is not assigned to a port pin when the SPI is placed in 3-wire mode
3
P1
4
5
6
for more information about the External Memory Interface.
7
Muxed Addr H/Non-muxed Addr L
z
z z
z z z
z z z z
z z z z z
z z z z z z
z z z z z z z
z z z z z z z z
z z z z z z z z z
z z z z z z z z z z
z z z z z z z z z z z
z z z z z z z z z z z z
z z z z z z z z z z z z z
z z z z z z z z z z z z z z
z z z z z z z z z z z z z z z
z z z z z z z z z z z z z z z z
z z z z z z z z z z z z z z z z
z z z z z z z z z z z z z z z z
z z z z z z z z z z z z z z z z
z z z z z z z z z z z z z z z z
0
Rev. 1.5
1
2
3
P2
4
5
6
7
Section “16. External Data Memory
0
Muxed Data/Non-muxed Data
1
2
3
P3
4
5
6
7
Crossbar Register Bits
UART0EN:
UART1EN:
CNVSTE0: XBR2.0
CNVSTE2: XBR3.2
SMB0EN:
PCA0ME:
SYSCKE: XBR1.7
SPI0EN:
T2EXE: XBR1.6
T3EXE: XBR3.1
T4EXE: XBR2.4
ECI0E: XBR0.6
INT0E: XBR1.2
INT1E: XBR1.4
CP0E: XBR0.7
CP1E: XBR1.0
CP2E: XBR3.3
T0E: XBR1.1
T1E: XBR1.3
T2E: XBR1.5
T3E: XBR3.0
T4E: XBR2.3
XBR0.2
XBR0.1
XBR0.0
XBR2.2
XBR0.[5:3]