SAB80C537-N Infineon Technologies, SAB80C537-N Datasheet - Page 48

no-image

SAB80C537-N

Manufacturer Part Number
SAB80C537-N
Description
IC MIRCROCONTROLLER 8BIT 84PLCC
Manufacturer
Infineon Technologies
Datasheet

Specifications of SAB80C537-N

Core Processor
8051
Core Size
8-Bit
Speed
12MHz
Connectivity
EBI/EMI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Type
ROMless
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x8b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
84-LCC (J-Lead)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
Q1612975

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SAB80C537-N
Manufacturer:
INFINEON
Quantity:
1 388
Part Number:
SAB80C537-N
Manufacturer:
Infineon
Quantity:
1 349
Part Number:
SAB80C537-N
Manufacturer:
Infineon Technologies
Quantity:
10 000
Company:
Part Number:
SAB80C537-N,,780,INFINEON/Ӣ
0
Part Number:
SAB80C537-NT40/85
Manufacturer:
Infineon
Quantity:
1 347
Notes for pages 44, 45 and 46:
1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed
2) Capacitive loading on ports 0 and 2 may cause the V
3) Power down I
4) I
5) I
6) I
7) The output impedance of the analog source must be low enough to assure full loading of the
8) The differential impedance
9) Exceeding the limit values at one or more input channels will cause additional current which
10) Only valid for not selected analog inputs.
11) No missing code.
Semiconductor Group
on the V
discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during
bus operation.
In the worst case (capacitive loading > 100 pF), the noise pulse on ALE line may exceed
0.8 V. In such cases it may be desirable to qualify ALE with a schmitt-trigger, or use an
address latch with a schmitt- trigger strobe input.
fall below the 0.9 V
EA = RESET = V
V
signal according to the figure below; XTAL1 = N.C.;
EA = OWE = PE/SWD = V
RESET = V
disabled; XTAL2 driven with clock signal according to the figure below; XTAL1 = N.C.;
RESET = OWE = V
I
disabled;
Port 7 = Port 8 = V
idle mode: I
Where f
V
sample capacitance (C
in the load time (T
(T
1 k at reference supply voltage.
is sinked sourced at these channels. This may also affect the accuracy of other channels
which are operated within the specification.
C C
CC
CC
CC
AGND
CC
S
).
(idle mode,) is measured with all output pins disconnected and with all peripherals
(slow down mode) is measured with all output pins disconnected and with all peripherals
(active mode) is measured with all output pins disconnected; XTAL2 driven with clock
(max.) at other frequencies is given by: active mode: I
= 5 V (see also notes 4 and 5).
= N.C.; V
OSC
OL
SS
XTAL2 driven with clock signal according to the figure below; XTAL = N.C.;
of ALE and ports 1, 3, 4, 5 and 6. The noise is due to external bus capacitance
CC
is the oscillator frequency in MHz. I
PD
. I
max = 1.0
AREF
CC
is measured with all output pins disconnected;
CC
L
CC
would be slightly higher if a crystal oscillator is used.
) the analog input must be held constant for the rest of the sample time
CC
CC
; Port 0 = Port 7 = Port 8 = V
= V
;
; Port 0 = Port 7 = Port 8 = V
specification when the address lines are stabilizing.
I
) during load time (T
CC
EA = PE/SWD = V
*
CC
f
; PE/SWD = OWE = V
OSC
R
; Port 0 = Port 7 = Port 8 = V
D
of the analog reference voltage source must be less than
+ 3.0
47
L
). After charging of the internal capacitance (C
SS
.
CC
CC
SS
values are given in mA and measured at
CC
; XTAL1 = N.C.; XTAL2 = V
.
OH
; EA = PE/SWD = V
on ALE and PSEN to momentarily
CC
CC
;
max = 3.1
SAB 80C517/80C537
*
SS
f
OSC
.
SS
+ 3.0
;
I
)