IC 80C51 MCU FLASH 8K 28-TSSOP

P89LPC932A1FDH,512

Manufacturer Part NumberP89LPC932A1FDH,512
DescriptionIC 80C51 MCU FLASH 8K 28-TSSOP
ManufacturerNXP Semiconductors
SeriesLPC900
P89LPC932A1FDH,512 datasheet
 


Specifications of P89LPC932A1FDH,512

Program Memory TypeFLASHProgram Memory Size8KB (8K x 8)
Package / Case28-TSSOPCore Processor8051
Core Size8-BitSpeed18MHz
ConnectivityI²C, SPI, UART/USARTPeripheralsBrown-out Detect/Reset, LED, POR, PWM, WDT
Number Of I /o26Ram Size768 x 8
Voltage - Supply (vcc/vdd)2.4 V ~ 3.6 VOscillator TypeInternal
Operating Temperature-40°C ~ 85°CProcessor SeriesP89LPC9x
Core80C51Data Bus Width8 bit
Data Ram Size768 BInterface TypeI2C/SPI/UART
Maximum Clock Frequency18 MHzNumber Of Programmable I/os26
Number Of Timers2Operating Supply Voltage2.4 V to 3.6 V
Maximum Operating Temperature+ 85 CMounting StyleSMD/SMT
3rd Party Development ToolsPK51, CA51, A51, ULINK2Minimum Operating Temperature- 40 C
Cpu Family89LPDevice Core80C51
Device Core Size8bFrequency (max)18MHz
Total Internal Ram Size768Byte# I/os (max)26
Number Of Timers - General Purpose2Operating Supply Voltage (typ)2.5/3.3V
Operating Supply Voltage (max)3.6VOperating Supply Voltage (min)2.4V
Instruction Set ArchitectureCISCOperating Temp Range-40C to 85C
Operating Temperature ClassificationIndustrialMountingSurface Mount
Pin Count28Package TypeTSSOP
Lead Free Status / RoHS StatusLead free / RoHS CompliantFor Use WithOM6292 - DEMO BOARD PCA2125 RTCDB-TSSOP-LPC932 - BOARD FOR LPC932 TSSOP622-1014 - BOARD FOR LPC9XX TSSOP622-1008 - BOARD FOR LPC9103 10-HVSON622-1006 - SOCKET ADAPTER BOARDMCB900K - BOARD PROTOTYPE NXP 89LPC9EPM900K - EMULATOR/PROGRAMMER NXP P89LPC9568-4000 - DEMO BOARD SPI/I2C TO DUAL UART568-3510 - DEMO BOARD SPI/I2C TO UART622-1003 - KIT FOR LCD DEMO622-1002 - USB IN-CIRCUIT PROG LPC9XX568-1759 - EMULATOR DEBUGGER/PROGRMMR LPC9X568-1758 - BOARD EVAL FOR LPC93X MCU FAMILY
Eeprom Size-Data Converters-
Other names568-4515-5
935276132512
P89LPC932A1FDH
P89LPC932A1FDH
  
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P89LPC932A1
8-bit microcontroller with accelerated two-clock 80C51 core
8 kB 3 V byte-erasable flash with 512-byte data EEPROM
Rev. 03 — 12 March 2007
1. General description
The P89LPC932A1 is a single-chip microcontroller, available in low cost packages, based
on a high performance processor architecture that executes instructions in two to four
clocks, six times the rate of standard 80C51 devices. Many system-level functions have
been incorporated into the P89LPC932A1 in order to reduce component count, board
space, and system cost.
2. Features
2.1 Principal features
I
8 kB byte-erasable flash code memory organized into 1 kB sectors and 64-byte pages.
Single-byte erasing allows any byte(s) to be used as non-volatile data storage.
I
256-byte RAM data memory, 512-byte auxiliary on-chip RAM.
I
512-byte customer data EEPROM on chip allows serialization of devices, storage of
set-up parameters, etc.
I
Two analog comparators with selectable inputs and reference source.
I
Two 16-bit counter/timers (each may be configured to toggle a port output upon timer
overflow or to become a PWM output) and a 23-bit system timer that can also be used
as a RTC.
I
Enhanced UART with fractional baud rate generator, break detect, framing error
detection, and automatic address detection; 400 kHz byte-wide I
communication port and SPI communication port.
I
CCU provides PWM, input capture, and output compare functions.
I
High-accuracy internal RC oscillator option allows operation without external oscillator
components. The RC oscillator option is selectable and fine tunable.
I
2.4 V to 3.6 V V
driven to 5.5 V).
I
28-pin TSSOP, PLCC, HVQFN, and DIP packages with 23 I/O pins minimum and up to
26 I/O pins while using on-chip oscillator and reset options.
2.2 Additional features
I
A high performance 80C51 CPU provides instruction cycle times of 111 ns to 222 ns
for all instructions except multiply and divide when executing at 18 MHz. This is six
times the performance of the standard 80C51 running at the same clock frequency. A
lower clock frequency for the same performance results in power savings and reduced
EMI.
operating range. I/O pins are 5 V tolerant (may be pulled up or
DD
Product data sheet
2
C-bus

P89LPC932A1FDH,512 Summary of contents

  • Page 1

    P89LPC932A1 8-bit microcontroller with accelerated two-clock 80C51 core byte-erasable flash with 512-byte data EEPROM Rev. 03 — 12 March 2007 1. General description The P89LPC932A1 is a single-chip microcontroller, available in low cost packages, based on ...

  • Page 2

    ... NXP Semiconductors I In-Circuit Programming (ICP) allows simple production coding with commercial EPROM programmers. Flash security bits prevent reading of sensitive application programs. I Serial flash In-System Programming (ISP) allows coding while the device is mounted in the end application. I In-Application Programming (IAP) of the flash code memory. This allows changing the code in a running application ...

  • Page 3

    ... NXP Semiconductors I The RCCLK bit has been added to the TRIM register allowing the RCCLK to be selected as the CPU clock (CCLK) regardless of the settings in UCFG1, allowing the internal RC oscillator to be selected as the CPU clock without the need to reset the device. I Enhancements added to the ISP/IAP code to improve code safety and increase ISP/IAP functionality ...

  • Page 4

    ... NXP Semiconductors 4. Block diagram P3[1:0] P2[7:0] P1[7:0] P0[7:0] XTAL1 CRYSTAL OR RESONATOR XTAL2 Fig 1. Block diagram P89LPC932A1_3 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core P89LPC932A1 ACCELERATED 2-CLOCK 80C51 CPU 8 kB CODE FLASH internal bus 256-BYTE DATA RAM 512-BYTE AUXILIARY RAM ...

  • Page 5

    ... NXP Semiconductors 5. Functional diagram CLKOUT Fig 2. Functional diagram of P89LPC932A1 6. Pinning information 6.1 Pinning Fig 3. P89LPC932A1 TSSOP28 pin configuration P89LPC932A1_3 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core KBI0 CMP2 KBI1 CIN2B KBI2 CIN2A KBI3 CIN1B PORT 0 KBI4 CIN1A ...

  • Page 6

    ... NXP Semiconductors Fig 4. P89LPC932A1 PLCC28 pin configuration Fig 5. P89LPC932A1 HVQFN28 pin configuration P89LPC932A1_3 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core 5 P1.6/OCB P1.5/RST P89LPC932A1FA 8 P3.1/XTAL1 9 P3.0/XTAL2/CLKOUT P1.4/INT1 10 P1.3/INT0/SDA 11 terminal 1 index area 1 P1.6/OCB 2 P1.5/RST P89LPC932A1FHN 4 P3.1/XTAL1 5 P3.0/XTAL2/CLKOUT P1.4/INT1 ...

  • Page 7

    ... NXP Semiconductors Fig 6. P89LPC932A1 DIP28 pin configuration 6.2 Pin description Table 2. Pin description Symbol Pin TSSOP28, HVQFN28 PLCC28, DIP28 P0.0 to P0.7 P0.0/CMP2 KBI0 P0.1/CIN2B KBI1 P0.2/CIN2A KBI2 P0.3/CIN1B KBI3 P89LPC932A1_3 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core 1 P2 ...

  • Page 8

    ... NXP Semiconductors Table 2. Pin description …continued Symbol Pin TSSOP28, HVQFN28 PLCC28, DIP28 P0.4/ CIN1A KBI4 P0. CMPREF/ KBI5 P0.6/CMP1 KBI6 P0.7/T1/KBI7 19 15 P1.0 to P1.7 P1.0/TXD 18 14 P1.1/RXD 17 13 P1.2/T0/SCL 12 8 P1.3/INT0 SDA P1.4/INT1 10 6 P89LPC932A1_3 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core ...

  • Page 9

    ... NXP Semiconductors Table 2. Pin description …continued Symbol Pin TSSOP28, HVQFN28 PLCC28, DIP28 P1.5/RST 6 2 P1.6/OCB 5 1 P1.7/OCC 4 28 P2.0 to P2.7 P2.0/ICB 1 25 P2.1/OCD 2 26 P2.2/MOSI 13 9 P2.3/MISO 14 10 P2.4/ P2.5/SPICLK 16 12 P2.6/OCA 27 23 P89LPC932A1_3 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core ...

  • Page 10

    ... NXP Semiconductors Table 2. Pin description …continued Symbol Pin TSSOP28, HVQFN28 PLCC28, DIP28 P2.7/ICA 28 24 P3.0 to P3.1 P3.0/XTAL2 CLKOUT P3.1/XTAL1 [1] Input/Output for P1.0 to P1.4, P1.6, P1.7. Input for P1.5. P89LPC932A1_3 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core Type Description I/O P2.7 — ...

  • Page 11

    ... NXP Semiconductors 7. Functional description Remark: Please refer to the P89LPC932A1 User manual for a more detailed functional description. 7.1 Special function registers Remark: Special Function Registers (SFRs) accesses are restricted in the following ways: • User must not attempt to access any SFR locations not defined. ...

  • Page 12

    Table 3. Special function registers * indicates SFRs that are bit addressable. Name Description SFR addr. Bit address ACC* Accumulator E0H AUXR1 Auxiliary function register A2H Bit address B* B register F0H BRGR0 Baud rate generator rate low BEH BRGR1 ...

  • Page 13

    Table 3. Special function registers …continued * indicates SFRs that are bit addressable. Name Description SFR addr. 2 I2DAT I C data register DAH I2SCLH Serial clock generator/SCL DDH duty cycle register high I2SCLL Serial clock generator/SCL DCH duty cycle ...

  • Page 14

    Table 3. Special function registers …continued * indicates SFRs that are bit addressable. Name Description SFR addr. OCRBH Output compare B register FBH high OCRBL Output compare B register FAH low OCRCH Output compare C register FDH high OCRCL Output ...

  • Page 15

    Table 3. Special function registers …continued * indicates SFRs that are bit addressable. Name Description SFR addr. PCONA Power control register A B5H Bit address PSW* Program status word D0H PT0AD Port 0 digital input disable F6H RSTSRC Reset source ...

  • Page 16

    Table 3. Special function registers …continued * indicates SFRs that are bit addressable. Name Description SFR addr. TISE2 CCU interrupt status encode DEH register TL0 Timer 0 low 8AH TL1 Timer 1 low 8BH TL2 CCU timer low CCH TMOD ...

  • Page 17

    ... NXP Semiconductors 7.2 Enhanced CPU The P89LPC932A1 uses an enhanced 80C51 CPU which runs at six times the speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most instructions execute in one or two machine cycles. 7.3 Clocks 7.3.1 Clock definitions The P89LPC932A1 device has several internal clocks as defined below: OSCCLK — ...

  • Page 18

    ... NXP Semiconductors The frequency of this clock output is in Idle mode, it may be turned off prior to entering Idle, saving additional power. 7.4 On-chip RC oscillator option The P89LPC932A1 has a 6-bit TRIM register that can be used to tune the frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory preprogrammed value to adjust the oscillator frequency to 7 ...

  • Page 19

    ... NXP Semiconductors 7.7 CCLK wake-up delay The P89LPC932A1 has an internal wake-up timer that delays the clock until it stabilizes depending on the clock source used. If the clock source is any of the three crystal selections (low, medium and high frequencies) the delay is 992 OSCCLK cycles plus 100 s ...

  • Page 20

    ... NXP Semiconductors • CODE Code memory space, accessed as part of program execution and via the MOVC instruction. The P89LPC932A1 has on-chip Code memory. The P89LPC932A1 also has 512 bytes of on-chip Data EEPROM that is accessed via SFRs (see 7.11 Data RAM arrangement The 768 bytes of on-chip RAM are organized as shown in Table 4 ...

  • Page 21

    ... NXP Semiconductors In edge-triggered mode, if successive samples of the INTn pin show a HIGH in one cycle and a LOW in the next cycle, the interrupt request flag IEn in TCON is set, causing an interrupt request external interrupt is enabled when the P89LPC932A1 is put into Power-down or Idle mode, the interrupt will cause the processor to wake-up and resume operation. Refer to Section 7.15 “ ...

  • Page 22

    ... NXP Semiconductors Table 5. Number of I/O pins available Clock source External clock input Low/medium/high speed oscillator (external crystal or resonator) [1] Required for operation above 12 MHz. 7.13.1 Port configurations All but three I/O port pins on the P89LPC932A1 may be configured by software to one of four types on a bit-by-bit basis. These are: quasi-bidirectional (standard 80C51 port outputs), push-pull, open drain, and input-only. Two confi ...

  • Page 23

    ... NXP Semiconductors 7.13.1.4 Push-pull output configuration The push-pull output configuration has the same pull-down structure as both the open-drain and the quasi-bidirectional output modes, but provides a continuous strong pull-up when the port latch contains a logic 1. The push-pull mode may be used when more source current is needed from a port output ...

  • Page 24

    ... NXP Semiconductors For correct activation of brownout detect, the V Please see 7.14.2 Power-on detection The Power-on detect has a function similar to the brownout detect, but is designed to work as power comes up initially, before the power supply voltage reaches a level where brownout detect can work. The POF flag in the RSTSRC register is set to indicate an initial power-up condition. The POF fl ...

  • Page 25

    ... NXP Semiconductors After power-up this input will function either as an external reset input digital input as defined by the RPE bit. Only a power-up reset will temporarily override the selection defined by RPE bit. Other sources of reset will not override the RPE bit. Reset can be triggered from the following sources: • ...

  • Page 26

    ... NXP Semiconductors 7.17.2 Mode 1 Mode 1 is the same as Mode 0, except that all 16 bits of the timer register are used. 7.17.3 Mode 2 Mode 2 configures the Timer register as an 8-bit Counter with automatic reload. Mode 2 operation is the same for Timer 0 and Timer 1. 7.17.4 Mode 3 When Timer Mode stopped ...

  • Page 27

    ... NXP Semiconductors 7.19 CCU This unit features: • A 16-bit timer with 16-bit reload on overflow. • Selectable clock, with prescaler to divide clock source by any integral number between 1 and 1024. • Four Compare/PWM outputs with selectable polarity • Symmetrical/Asymmetrical PWM selection • ...

  • Page 28

    ... NXP Semiconductors 7.19.6 PWM operation PWM operation has two main modes, symmetrical and asymmetrical. In asymmetrical PWM operation the CCU Timer operates in down-counting mode regardless of the direction control bit. In symmetrical mode, the timer counts up/down alternately. The main difference from basic timer operation is the operation of the compare module, which in PWM mode is used for PWM waveform generation ...

  • Page 29

    ... NXP Semiconductors 7.19.7 Alternating output mode In asymmetrical mode, the user can set up PWM channels A/B and C/D as alternating pairs for bridge drive control. In this mode the output of these PWM channels are alternately gated on every counter cycle. Fig 11. Alternate output mode 7.19.8 PLL operation The PWM module features a PLL that can be used to generate a CCUCLK frequency between 16 MHz and 32 MHz ...

  • Page 30

    ... NXP Semiconductors 7.19.9 CCU interrupts There are seven interrupt sources on the CCU which share a common interrupt vector. EA (IEN0.7) ECCU (IEN1.4) TOIE2 (TICR2.7) TOIF2 (TIFR2.7) TICIE2A (TICR2.0) TICF2A (TIFR2.0) TICIE2B (TICR2.1) TICF2B (TIFR2.1) TOCIE2A (TICR2.3) TOCF2A (TIFR2.3) TOCIE2B (TICR2.4) TOCF2B (TIFR2.4) TOCIE2C (TICR2.5) TOCF2C (TIFR2 ...

  • Page 31

    ... NXP Semiconductors 7.20.3 Mode 2 11 bits are transmitted (through TXD) or received (through RXD): start bit (logic 0), 8 data bits (LSB first), a programmable 9 transmitted, the 9 Or, for example, the parity bit (P, in the PSW) could be moved into TB8. When data is received, the 9 bit is not saved ...

  • Page 32

    ... NXP Semiconductors 7.20.8 Double buffering The UART has a transmit double buffer that allows buffering of the next character to be written to SBUF while the first character is being transmitted. Double buffering allows transmission of a string of characters with only one stop bit between any two characters, as long as the next character is written between the start bit and the stop bit of the previous character ...

  • Page 33

    ... NXP Semiconductors 2 7.21 I C-bus serial interface 2 The I C-bus uses two wires (SDA and SCL) to transfer information between devices connected to the bus, and it has the following features: • Bidirectional data transfer between masters and slaves. • Multi master bus (no central master). • ...

  • Page 34

    ... NXP Semiconductors P1.3/SDA P1.2/SCL Fig 15. I P89LPC932A1_3 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core P1.3 INPUT FILTER OUTPUT STAGE INPUT FILTER OUTPUT STAGE timer 1 overflow P1.2 I2CON I2SCLH I2SCLL status bus I2STAT 2 C-bus serial interface block diagram Rev. 03 — 12 March 2007 ...

  • Page 35

    ... NXP Semiconductors 7.22 Serial Peripheral Interface (SPI) The P89LPC932A1 provides another high-speed serial communication interface—the SPI interface. SPI is a full-duplex, high-speed, synchronous communication bus with two operation modes: Master mode and Slave mode Mbit/s can be supported in Master mode Mbit/s in Slave mode. It has a Transfer Completion Flag and Write Collision Flag Protection ...

  • Page 36

    ... NXP Semiconductors 7.22.1 Typical SPI configurations Fig 17. SPI single master single slave configuration Fig 18. SPI dual device configuration, where either can be a master or a slave P89LPC932A1_3 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core master MISO ...

  • Page 37

    ... NXP Semiconductors Fig 19. SPI single master multiple slaves configuration P89LPC932A1_3 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core master MISO 8-BIT SHIFT MOSI REGISTER SPICLK SPI CLOCK port GENERATOR port Rev. 03 — 12 March 2007 P89LPC932A1 slave MISO 8-BIT SHIFT ...

  • Page 38

    ... NXP Semiconductors 7.23 Analog comparators Two analog comparators are provided on the P89LPC932A1. Input and output options allow use of the comparators in a number of different configurations. Comparator operation is such that the output is a logic 1 (which may be read in a register and/or routed to a pin) when the positive input (one of two selectable pins) is greater than the negative input (selectable from a pin or an internal reference voltage). Otherwise the output is a zero. Each comparator may be confi ...

  • Page 39

    ... NXP Semiconductors 7.23.3 Comparators and power reduction modes Either or both comparators may remain enabled when Power-down or Idle mode is activated, but both comparators are disabled automatically in Total Power-down mode comparator interrupt is enabled (except in Total Power-down mode), a change of the comparator output state will generate an interrupt and wake up the processor. If the comparator output to a pin is enabled, the pin should be confi ...

  • Page 40

    ... NXP Semiconductors 7.25 Watchdog timer The watchdog timer causes a system reset when it underflows as a result of a failure to feed the timer prior to the timer reaching its terminal count. It consists of a programmable 12-bit prescaler, and an 8-bit down counter. The down counter is decremented by a tap taken from the prescaler ...

  • Page 41

    ... NXP Semiconductors 7.27 Data EEPROM The P89LPC932A1 has 512 B of on-chip data EEPROM. The data EEPROM is SFR based, byte readable, byte writable, and erasable (via row fill and sector fill). The user can read, write and fill the memory via SFRs and one interrupt. This data EEPROM provides 400000 minimum erase/program cycles for each byte. • ...

  • Page 42

    ... NXP Semiconductors 7.28.3 Flash organization The program memory consists of eight 1 kB sectors on the P89LPC932A1 device. Each sector can be further divided into 64-byte pages. In addition to sector erase, page erase, and byte erase, a 64-byte page register is included which allows from 1 byte to 64 bytes of a given page to be programmed at the same time, substantially reducing overall programming time ...

  • Page 43

    ... NXP Semiconductors In addition, IAP operations can be accomplished through the use of four SFRs consisting of a control/status register, a data register, and two address registers. Additional details may be found in the P89LPC932A1 User manual . 7.28.8 In-system programming ISP is performed without removing the microcontroller from the system. The ISP facility consists of a series of internal hardware resources coupled with internal fi ...

  • Page 44

    ... NXP Semiconductors 7.29 User configuration bytes Some user-configurable features of the P89LPC932A1 must be defined at power-up and therefore cannot be set by the program after start of execution. These features are configured through the use of the flash byte UCFG1. Please see the P89LPC932A1 User manual for additional details ...

  • Page 45

    ... NXP Semiconductors 8. Limiting values Table 7. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter T operating bias ambient temperature amb(bias) T storage temperature range stg I HIGH-level output current per I/O pin OH(I/O) I LOW-level output current per I/O pin OL(I/O) ...

  • Page 46

    ... NXP Semiconductors 9. Static characteristics Table 8. Static characteristics 3.6 V unless otherwise specified +85 C for industrial applications, unless otherwise specified. amb Symbol Parameter I operating supply current DD(oper) I Idle mode supply current DD(idle) I power supply current, DD(pd) Power-down mode, voltage comparators powered-down ...

  • Page 47

    ... NXP Semiconductors Table 8. Static characteristics 3.6 V unless otherwise specified +85 C for industrial applications, unless otherwise specified. amb Symbol Parameter I logical 1-to-0 transition current, TL all ports R internal pull-up resistance on pin RST(int) RST V brownout trip voltage bo V band gap reference voltage ...

  • Page 48

    ... NXP Semiconductors 10. Dynamic characteristics Table 9. Dynamic characteristics (12 MHz 2 3.6 V unless otherwise specified +85 C for industrial applications, unless otherwise specified. amb Symbol Parameter f internal RC oscillator frequency OSC(RC) f internal watchdog oscillator OSC(WD) frequency f oscillator frequency osc T clock cycle time cy(CLK) f low power select clock frequency CLKLP Glitch fi ...

  • Page 49

    ... NXP Semiconductors Table 9. Dynamic characteristics (12 MHz 2 3.6 V unless otherwise specified +85 C for industrial applications, unless otherwise specified. amb Symbol Parameter t SPI enable lag time SPILAG 2.0 MHz (slave) t SPICLK HIGH time SPICLKH master slave t SPICLK LOW time SPICLKL master ...

  • Page 50

    ... NXP Semiconductors Table 10. Dynamic characteristics (18 MHz 3 3.6 V unless otherwise specified +85 C for industrial applications, unless otherwise specified. amb Symbol Parameter f internal RC oscillator frequency OSC(RC) f internal watchdog oscillator OSC(WD) frequency f oscillator frequency osc T clock cycle time cy(CLK) f low power select clock frequency CLKLP Glitch fi ...

  • Page 51

    ... NXP Semiconductors Table 10. Dynamic characteristics (18 MHz 3 3.6 V unless otherwise specified +85 C for industrial applications, unless otherwise specified. amb Symbol Parameter t SPICLK HIGH time SPICLKH master slave t SPICLK LOW time SPICLKL master slave t SPI data set-up time (master or SPIDSU slave) ...

  • Page 52

    ... NXP Semiconductors 10.1 Waveforms clock t QVXH output data write to SBUF t XHDV input data clear RI Fig 22. Shift register mode timing V 0 0.2V 0.2V 0.45 V Fig 23. External clock timing SS SPICLK (CPOL = 0) (output) SPICLK (CPOL = 1) (output) MISO (input) t MOSI SPIF (output) Fig 24. SPI master timing (CPHA = 0) ...

  • Page 53

    ... NXP Semiconductors SS SPICLK (CPOL = 0) (output) SPICLK (CPOL = 1) (output) MISO (input) t SPIF MOSI (output) Fig 25. SPI master timing (CPHA = SPIR t SPILEAD SPICLK (CPOL = 0) (input) t SPIF SPICLK (CPOL = 1) (input) t SPIA MISO (output) t SPIDSU MOSI (input) Fig 26. SPI slave timing (CPHA = 0) P89LPC932A1_3 Product data sheet ...

  • Page 54

    ... NXP Semiconductors SS t SPIR t SPILEAD SPICLK (CPOL = 0) (input) t SPIF SPICLK (CPOL = 1) (input) t SPIOH t SPIDV t SPIA MISO not defined (output) MOSI (input) Fig 27. SPI slave timing (CPHA = 1) 10.2 ISP entry mode Table 11. Dynamic characteristics, ISP entry mode 3.6 V, unless otherwise specified. ...

  • Page 55

    ... NXP Semiconductors 11. Other characteristics 11.1 Comparator electrical characteristics Table 12. Comparator electrical characteristics 3.6 V, unless otherwise specified +85 C for industrial applications, unless otherwise specified. amb Symbol Parameter V input offset voltage IO V common-mode input voltage IC CMRR common-mode rejection ratio t total response time ...

  • Page 56

    ... NXP Semiconductors 12. Package outline PLCC28: plastic leaded chip carrier; 28 leads pin 1 index DIMENSIONS (mm dimensions are derived from the original inch dimensions UNIT max. min. 4.57 0.53 mm 0.51 0.25 3.05 4.19 0.33 0.180 0.021 inches 0.02 0.01 0.12 0.165 0.013 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...

  • Page 57

    ... NXP Semiconductors TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...

  • Page 58

    ... NXP Semiconductors HVQFN28: plastic thermal enhanced very thin quad flat package; no leads; 28 terminals; body 0.85 mm terminal 1 index area terminal 1 28 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max. 0.05 0.35 mm 0.2 1 0.00 0.25 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. ...

  • Page 59

    ... NXP Semiconductors DIP28: plastic dual in-line package; 28 leads (600 mil pin 1 index 1 DIMENSIONS (mm dimensions are derived from the original inch dimensions UNIT max. min. max. mm 5.1 0.51 4 inches 0.2 0.02 0.16 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...

  • Page 60

    ... NXP Semiconductors 13. Abbreviations Table 13. Acronym CCU CPU CRC EPROM EEPROM EMI LED PLL PWM RAM RC RTC SFR SPI UART P89LPC932A1_3 Product data sheet 8-bit microcontroller with accelerated two-clock 80C51 core Acronym list Description Capture/Compare Unit Central Processing Unit Cyclic Redundancy Check ...

  • Page 61

    ... Release date P89LPC932A1_3 20070312 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Added new part type P89LPC932A1FN. P89LPC932A1_2 ...

  • Page 62

    ... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...

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    ... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 Principal features . . . . . . . . . . . . . . . . . . . . . . . 1 2.2 Additional features . . . . . . . . . . . . . . . . . . . . . . 1 2.3 Comparison to the P89LPC932 . . . . . . . . . . . . 2 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 5 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 Functional description . . . . . . . . . . . . . . . . . . 11 7.1 Special function registers . . . . . . . . . . . . . . . . 11 7 ...

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    ... NXP Semiconductors 7.28.3 Flash organization . . . . . . . . . . . . . . . . . . . . . 42 7.28.4 Using flash as data storage . . . . . . . . . . . . . . 42 7.28.5 Flash programming and erasing . . . . . . . . . . . 42 7.28.6 In-circuit programming . . . . . . . . . . . . . . . . . . 42 7.28.7 In-application programming . . . . . . . . . . . . . . 42 7.28.8 In-system programming . . . . . . . . . . . . . . . . . 43 7.28.9 Power-on reset code execution 7.28.10 Hardware activation of the boot loader . . . . . . 43 7.29 User configuration bytes . . . . . . . . . . . . . . . . . 44 7.30 User sector security bytes ...