LPC3130FET180,551 NXP Semiconductors, LPC3130FET180,551 Datasheet - Page 11

• Manufacturer Part Number: LPC3130FET180,551
• Description: IC ARM9 MCU 180MHZ 180-TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC3000r

Specifications of LPC3130FET180,551

• Package / Case: 180-TFBGA
• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, PWM, WDT
• Program Memory Type: ROMless
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC31
• Core: ARM926EJ-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 96 KB
• Interface Type: I2C/I2S/UART/USB
• Maximum Clock Frequency: 180 MHz
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 4-ch x 10-bit
• Cpu Family: LPC3000
• Device Core: ARM926EJ-S
• Device Core Size: 16/32Bit
• Frequency (max): 180MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 96KB
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.2/1.8/2.8/3.3/5V
• Operating Supply Voltage (max): 1.3/3.6V
• Operating Supply Voltage (min): 1/1.1/1.65/2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 180
• Package Type: TFBGA
• Package: 180TFBGA
• Family Name: LPC3000
• Maximum Speed: 180 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4850 - KIT EVAL FOR LPC313X568-4062 - DEBUGGER J-LINK JTAG568-4061 - DEBUGGER U-LINK2 JTAG FOR NXP
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4696; 935288013551; LPC3130FET180-S

NXP Semiconductors
Table 4.
Pin names with prefix m are multiplexed pins. See
[1]
[2]
[3]
[4]
LPC3130_3131
Preliminary data sheet
Pin name
External Bus Interface (NAND flash controller)
EBI_A_0_ALE
EBI_A_1_CLE
EBI_D_0
EBI_D_1
EBI_D_2
EBI_D_3
EBI_D_4
EBI_D_5
EBI_D_6
EBI_D_7
EBI_D_8
EBI_D_9
EBI_D_10
EBI_D_11
EBI_D_12
EBI_D_13
EBI_D_14
EBI_D_15
EBI_DQM_0_NOE
EBI_NWE
NAND_NCS_0
NAND_NCS_1
NAND_NCS_2
NAND_NCS_3
mNAND_RYBN0
mNAND_RYBN1
mNAND_RYBN2
mNAND_RYBN3
EBI_NCAS_BLOUT_0
EBI_NRAS_BLOUT_1
Pulse Width Modulation module
PWM_DATA
Digital I/O levels are explained in
I = input; I:PU = input with internal weak pull-up; I:PD = input with internal weak pull-down; O = output.
Cell types are explained in
Pin can be configured as GPIO pin in the IOCONFIG block.
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
Pin description
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
BGA
ball
B3
A2
G2
F2
F1
E1
E2
D1
D2
C1
B1
A3
A1
C2
G3
D3
E3
F3
H1
J2
J1
J3
K1
K2
E6
E7
B4
D4
G1
H2
B9
Table
6.
Digital
I/O
level
[1]
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP3
Table
5.
All information provided in this document is subject to legal disclaimers.
Application
function
DO
DO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DO
DO
DO
DO
DO
DO
DI
DI
DI
DI
DO
DO
DO / GPIO
Rev. 1.04 — 27 May 2010
Table 10
Pin
state
after
reset
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O
O
O
O
O
O
I
I
I
I
O
O
O
for pin function selection of multiplexed pins.
Low-cost, low-power ARM926EJ-S microcontrollers
[2]
Cell type
[3]
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO1
Description
EBI Address Latch Enable
EBI Command Latch Enable
EBI Data I/O 0
EBI Data I/O 1
EBI Data I/O 2
EBI Data I/O 3
EBI Data I/O 4
EBI Data I/O 5
EBI Data I/O 6
EBI Data I/O 7
EBI Data I/O 8
EBI Data I/O 9
EBI Data I/O 10
EBI Data I/O 11
EBI Data I/O 12
EBI Data I/O 13
EBI Data I/O 14
EBI Data I/O 15
NAND Read Enable (active LOW)
NAND Write Enable (active LOW)
NAND Chip Enable 0
NAND Chip Enable 1
NAND Chip Enable 2
NAND Chip Enable 3
NAND Ready/Busy 0
NAND Ready/Busy 1
NAND Ready/Busy 2
NAND Ready/Busy 3
EBI Lower lane byte select (7:0)
EBI Upper lane byte select (15:8)
PWM Output
LPC3130/3131
© NXP B.V. 2010. All rights reserved.
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