LPC3130FET180,551 NXP Semiconductors, LPC3130FET180,551 Datasheet - Page 35

• Manufacturer Part Number: LPC3130FET180,551
• Description: IC ARM9 MCU 180MHZ 180-TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC3000r

Specifications of LPC3130FET180,551

• Package / Case: 180-TFBGA
• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, PWM, WDT
• Program Memory Type: ROMless
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC31
• Core: ARM926EJ-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 96 KB
• Interface Type: I2C/I2S/UART/USB
• Maximum Clock Frequency: 180 MHz
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 4-ch x 10-bit
• Cpu Family: LPC3000
• Device Core: ARM926EJ-S
• Device Core Size: 16/32Bit
• Frequency (max): 180MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 96KB
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.2/1.8/2.8/3.3/5V
• Operating Supply Voltage (max): 1.3/3.6V
• Operating Supply Voltage (min): 1/1.1/1.65/2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 180
• Package Type: TFBGA
• Package: 180TFBGA
• Family Name: LPC3000
• Maximum Speed: 180 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4850 - KIT EVAL FOR LPC313X568-4062 - DEBUGGER J-LINK JTAG568-4061 - DEBUGGER U-LINK2 JTAG FOR NXP
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4696; 935288013551; LPC3130FET180-S

NXP Semiconductors
LPC3130_3131
Preliminary data sheet
6.29 System control registers
6.30 I2S0/1 interfaces
The System Control Registers (SysCReg) module provides a register interface for some
of the high-level settings in the system such as multiplexers and mode settings. This is an
auxiliary module included in this overview for the sake of completeness.
The I2S0/1 receive and I2S0/1 transmit modules have the following features:
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Audio interface compatible with the I
I2S0/1 receive supports master mode and slave mode.
I2S0/1 transmit supports master mode.
Supports LSB justified words of 16, 18, 20 and 24 bits.
Supports a configurable number of bit clock periods per Word Select period (up to
128 bit clock periods).
Supports DMA transfers.
Transmit FIFO (I
Supports single 16 bit transfers to/from the left or right FIFO.
Supports single 24 bit transfers to/from the left or right FIFO.
Supports 32-bit interleaved transfers, with the lower 16 bits representing the left audio
sample, and the higher 16 bits representing the right audio sample.
Supports two 16-bit audio samples combined in a 32-bit word (2 left or 2 right
samples) to reduce bus load.
Provides maskable interrupts for audio status: FIFO underrun/overrun/full/
half_full/not empty for left and right channel separately.
All information provided in this document is subject to legal disclaimers.
2
S transmit) or receive FIFO (I
Rev. 1.04 — 27 May 2010
Low-cost, low-power ARM926EJ-S microcontrollers
2
S standard.
2
S receive) of 4 stereo samples.
LPC3130/3131
© NXP B.V. 2010. All rights reserved.
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