LPC3130FET180,551 NXP Semiconductors, LPC3130FET180,551 Datasheet - Page 62

• Manufacturer Part Number: LPC3130FET180,551
• Description: IC ARM9 MCU 180MHZ 180-TFBGA
• Manufacturer: NXP Semiconductors
• Series: LPC3000r

Specifications of LPC3130FET180,551

• Package / Case: 180-TFBGA
• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, PWM, WDT
• Program Memory Type: ROMless
• Ram Size: 96K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 4x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: LPC31
• Core: ARM926EJ-S
• Data Bus Width: 16 bit, 32 bit
• Data Ram Size: 96 KB
• Interface Type: I2C/I2S/UART/USB
• Maximum Clock Frequency: 180 MHz
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 4-ch x 10-bit
• Cpu Family: LPC3000
• Device Core: ARM926EJ-S
• Device Core Size: 16/32Bit
• Frequency (max): 180MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 96KB
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 1.2/1.8/2.8/3.3/5V
• Operating Supply Voltage (max): 1.3/3.6V
• Operating Supply Voltage (min): 1/1.1/1.65/2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 180
• Package Type: TFBGA
• Package: 180TFBGA
• Family Name: LPC3000
• Maximum Speed: 180 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4850 - KIT EVAL FOR LPC313X568-4062 - DEBUGGER J-LINK JTAG568-4061 - DEBUGGER U-LINK2 JTAG FOR NXP
• Number Of I /o: -
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-4696; 935288013551; LPC3130FET180-S

NXP Semiconductors
Table 26.
C
[1]
LPC3130_3131
Preliminary data sheet
Symbol
t
t
t
V
t
t
t
t
t
t
r
f
FRFM
FEOPT
FDEOP
JR1
JR2
EOPR1
EOPR2
Fig 27. I
L
CRS
= 50 pF; R
Characterized but not implemented as production test. Guaranteed by design.
SDA
SCL
Remark: Signals SDA and SCL correspond to pins I2C_SDAx and I2C_SCLx (x = 0, 1).
2
C-bus pins clock timing
Dynamic characteristics: USB pins (high-speed)
P
pu
= 1.5 k
9.9 USB interface
t
Parameter
rise time
fall time
differential rise and fall time
matching
output signal crossover voltage
source SE0 interval of EOP
source jitter for differential transition
to SE0 transition
receiver jitter to next transition
receiver jitter for paired transitions
EOP width at receiver
EOP width at receiver
BUF
Ω
on D+ to V
S
t
HD;STA
t
LOW
DD(IO)
(SUP3), unless otherwise specified.
All information provided in this document is subject to legal disclaimers.
t
t
HD;STA
r
Rev. 1.04 — 27 May 2010
t
HIGH
10 % to 90 %
Conditions
10 % to 90 %
10 % to 90 %
see
see
must reject as
EOP; see
Figure 28
must accept as
EOP; see
Figure 28
t
r
/ t
Figure 28
Figure 28
f
Low-cost, low-power ARM926EJ-S microcontrollers
t
f
t
SU;DAT
S
t
[1]
[1]
SU;STA
Min
<tbd>
<tbd>
-
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
t
HD;STA
LPC3130/3131
Typ
-
-
-
-
-
-
-
-
-
-
© NXP B.V. 2010. All rights reserved.
Max
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
<tbd>
-
-
t
002aad985
SU;STO
P
62 of 72
Unit
ns
ns
%
V
ns
ns
ns
ns
ns
ns