EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 141

• Manufacturer Part Number: EP9302-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-CQZ

• Program Memory Type: ROMless
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Data Ram Size: 16 bit
• Interface Type: USB, USART, SPI
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 37
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1137

PwrCnt
DS785UM1
FIR_EN
31
15
Address:
Definition:
Bit Descriptions:
RSVD
30
14
BAUD
UART
29
13
USH_EN
28
12
RSTFLG:
TEST_RESET:
CLDFLG:
WDTFLG:
CHIPID:
CHIPMAN:
0x8093_0004 - Read / Write
The PwrCnt system control register is the Clock/Debug control status register.
RSVD:
DMA
M2M
CH1
27
11
DMA
M2M
CH0
26
10
Copyright 2007 Cirrus Logic
DMA
M2P
CH8
25
9
Reset flag. This bit is set if the user reset button has been
pressed; forcing the RSTOn input low. It is cleared by
writing to the STFClr location. On power-on-reset, it is
reset to 0b.
Test reset flag. This bit is set if the test reset has been
activated; it is cleared by writing to the STFClr location. On
power-on-reset, it is reset to 0b.
Cold start flag. This bit is set if the device has been reset
with a power-on-reset; it is cleared by writing to the STFClr
location. On power-on-reset, it is set to 1b.
Watchdog Timer flag. This bit is set if the Watchdog timer
resets the system. It is cleared by writing to the STFClr
location. It is reset to 0.
Chip ID bits. This 8-bit register determines the Chip
Identification for the device. For the device, this value is
0x20.
This 8-bit register determines the Chip Manufacturer ID for
the device. For the device, this value is 0x43.
Reserved. Unknown During Read.
DMA
M2P
CH9
24
8
RSVD
DMA
M2P
CH6
23
7
DMA
M2P
CH7
22
6
DMA
M2P
CH4
21
5
DMA
M2P
CH5
20
4
DMA
M2P
CH2
19
3
EP93xx User’s Guide
DMA
M2P
CH3
18
2
System Controller
DMA
M2P
CH0
17
1
DMA
M2P
CH1
16
0
5-15
5