EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 695

• Manufacturer Part Number: EP9302-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-CQZ

• Program Memory Type: ROMless
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Data Ram Size: 16 bit
• Interface Type: USB, USART, SPI
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 37
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1137

AC97RXCRx
DS785UM1
CM
31
15
Address:
Definition:
Bit Descriptions:
Address:
For words to be transmitted:
For received words:
The receive FIFO is 21 bits wide. The 21
read via the AC97ISR registers. The receive overrun error status bit is transferred down to
the FIFO buffer along with the overrun data value.
RSVD
30
14
• If the FIFOs are enabled, data written to this location is pushed onto the transmit FIFO.
• If the FIFOs are not enabled, data is stored in the transmitter holding register (the bottom
• If the FIFOs are enabled, the data received is pushed onto the receive FIFO.
• If the FIFOs are not enabled, the data received is stored in the receiving holding register
RSIZE
word of the transmit FIFO).
(the bottom word of the receive FIFO).
29
13
RX12
28
12
AC97DR1 - 0x8088_0000 - Read/Write
AC97DR2 - 0x8088_0020 - Read/Write
AC97DR3 - 0x8088_0040 - Read/Write
AC97DR4 - 0x8088_0060 - Read/Write
The AC97DR registers are read / write data registers that are normally 20 bits
wide. In 16-bit compact mode, all 32 available bits are used. This register is
zero at reset.
RSVD:
DATA:
AC97RXCR1 - 0x8088_0004 - Read/Write
AC97RXCR2 - 0x8088_0024 - Read/Write
AC97RXCR3 - 0x8088_0044 - Read/Write
AC97RXCR4 - 0x8088_0064 - Read/Write
RX11
27
11
RX10
26
10
Copyright 2007 Cirrus Logic
RX9
25
9
Reserved. Unknown During Read.
Write - Transmit FIFO: The AC97TXCR register qualifies
the data within the TX FIFO.
Read - Receive FIFO: The AC97RXCR register qualifies
the data within the FIFO.
RX8
24
8
st
bit, the receive overrun error status, can only be
RX7
23
7
TOC
RX6
22
6
RX5
21
5
RX4
20
4
RX3
19
3
EP93xx User’s Guide
RX2
18
2
AC’97 Controller
RX1
17
1
FDIS
REN
16
22-7
0
22