EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 185

• Manufacturer Part Number: EP9302-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-CQZ

• Program Memory Type: ROMless
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Data Ram Size: 16 bit
• Interface Type: USB, USART, SPI
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 37
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1137

DS785UM1
HDTV-2 LCD
HDTV-2 CRT
7.3.1 Hardware Blinking
7.2 Features
7.3 Raster Engine Features Overview
SXGA CRT
Display
Type
Since the frame buffer is stored in SDRAM memory, supporting displays with high frame rates
at high resolutions will not be practical and sometimes not possible without using displays
that have an integrated frame buffer.
The raster engine pipeline contains hardware pixel blinking logic. This circuitry will blink
pixels based on the Rate field in the
multiple or single bit planes may be used to specify blinking pixels by look up in the LUT. This
will allow the number of definable blinking pixels to range from all pixel combinations blinking
Note: Using the Maximum Resolution causes system performance to slow.
• Hardware pixel blinking
• Dual 256-color Look-up-tables (LUT)
• Grayscale/Color Generation for Monochrome/Passive Low Color Displays
• Flexible frame buffer architecture
• Supports video information in DIB (Device Independent Bitmap) format
• Hardware support for left and right panning of the displayed information
• Supports screen sizes up to 1280 x 1024 pixels, with a pixel depth of 4 bpp, 8 bpp, 16
• Pulse Width Modulated output that can be used to provide a DC voltage level for
• Hardware cursor support with bottom and right edge clipping performed by hardware
• 24-bit color depth, but only 18 bits is bond-out
Resolution
bpp, 24 bpp packed, or 32 bpp (24 bpp unpacked)
brightness control
Horizontal
1280 x 1024
1280 x 720
1280 x 720
x
Resolution
Table 7-1. Raster Engine Video Mode Output Examples
Vertical
Copyright 2007 Cirrus Logic
Video
Clock
(MHz)
Freq.
110
50
66
Raster Engine With Analog/LCD Integrated Timing and Interface
BlinkRate
8, 16, or 24
8, 16, or 24
Storage
Format
8, 16, or
Frame
Buffer
24bpp
bpp
bpp
register. For 4 bpp and 8 bpp modes, either
24-bit RGB
Display
Format
Analog
Analog
Data
Pixels
Clock
Shift
Per
1
1
1
Clock
(MHz)
Freq.
Pixel
Shift
NA
NA
50
EP93xx User’s Guide
Vertical
Frame
Rate
(Hz)
70
50
60
External
DAC
24-bits
External
DAC
Notes
7-3
7