EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 570

• Manufacturer Part Number: EP9302-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-CQZ

• Program Memory Type: ROMless
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Data Ram Size: 16 bit
• Interface Type: USB, USART, SPI
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 37
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1137

15
UART2Ctrl
15-12
UART2
EP93xx User’s Guide
31
15
Address:
Default:
Definition:
Bit Descriptions:
30
14
29
13
28
12
0x808D_0014 - Read/Write
0x0000_0000
UART Control Register
RSVD:
LBE:
RTIE:
TIE:
RIE:
MSIE:
RSVD
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Reserved. Unknown During Read.
Loopback Enable, for SIR and UART only.
1 - If the SIR Enable bit is also set to “1”, and register
UART2TMR bit 1 (SIRTEST) is set to “1”, the SIR output
path is inverted and fed through to the SIR input path. The
SIRTEST bit in the test register must be set to “1” to
override the normal half-duplex SIR operation. This should
be the requirement for accessing the test registers during
normal operation, and SIRTEST must be cleared to “0”
when loopback testing is finished. This feature reduces the
amount of external coupling required during system test.
0 - This bit is cleared to “0” on reset, which disables the
loopback mode.
Receive Timeout Enable. If this bit is set to “1”, the receive
timeout interrupt is enabled.
Transmit Interrupt Enable. If this bit is set to “1”, the
transmit interrupt is enabled.
Receive Interrupt Enable. If this bit is set to “1”, the receive
interrupt is enabled.
Modem Status Interrupt Enable. If this bit is set to “1”, the
modem status interrupt is enabled.
24
8
RSVD
LBE
23
7
RTIE
22
6
TIE
21
5
RIE
20
4
MSIE
19
3
SIRLP
18
2
SIREN
17
1
DS785UM1
UARTE
16
0