EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 310

• Manufacturer Part Number: EP9302-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-CQZ

• Program Memory Type: ROMless
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Data Ram Size: 16 bit
• Interface Type: USB, USART, SPI
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 37
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1137

9
9-8
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
9.1.4.3 Bit Order
9.1.4.4 Destination Address (DA) Filter
9.1.4.5 Perfect Address Filtering
The resultant 32 bit field is transmitted on the line with bit X
In compliance with ISO/IEC 8802-3 section 3.3, each byte is transmitted low order bit first,
except for the CRC, as noted in
There are two forms of destination address filtering performed by the MAC, perfect filtering,
where the address is checked for an exact match, and hashing, where the address is
checked for inclusion in a group. In addition there is a mode to accept all destination
addresses which is enabled via the RXCtl.PA bit.
The MAC includes four programmable perfect address filters, as well as the all ones filter for
broadcast frames. The RXCtl register is used to control whether a particular filter is used. The
filters themselves share the same address space and the value in the Address Filter Pointer
register determines which filter is being accessed at any time. The filters are arranged such
that the first is the normal MAC address for the interface, which is also used in the detection
of remote wake-up frames, and may be optionally used to detect pause (flow control) frames.
The primary purpose of the second filter is for the recognition of pause frames. This would
normally be programmed to correspond to the multicast address used for MAC control
frames. The third and fourth filters, provide extra optional address match capabilities, which
can provide the capability of adding extra individual addresses or of providing two multicast
address filters.
Direction of transmission
D0
Byte
Half-Word
D7 D8
Figure 9-5. Data Bit Transmission Order
Copyright 2007 Cirrus Logic
Section 9.1.4.2 on page
D15 D16
Word
9--7.
31
first through X
0
D31
last.
DS785UM1