EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 321

IC ARM9 SOC PROCESSOR 208LQFP

EP9302-CQZ

Manufacturer Part Number
EP9302-CQZ
Description
IC ARM9 SOC PROCESSOR 208LQFP
Manufacturer
Cirrus Logic Inc
Series
EP9r
Datasheets

Specifications of EP9302-CQZ

Program Memory Type
ROMless
Package / Case
208-LQFP
Core Processor
ARM9
Core Size
16/32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
Data Ram Size
16 bit
Interface Type
USB, USART, SPI
Maximum Clock Frequency
200 MHz
Number Of Programmable I/os
37
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
EDB9302A-Z
Controller Family/series
(ARM9)
No. Of I/o's
19
Ram Memory Size
16MB
Cpu Speed
200MHz
No. Of Timers
4
Embedded Interface Type
AC97, I2S, SPI, UART, USB
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1132 - KIT DEVELOPMENT EP9302 ARM9
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1137

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DS785UM1
EOF:
EOB:
AM:
RX_Err:
OE:
FE:
Runt:
EData:
CRCE:
CRCI:
Copyright 2007 Cirrus Logic
End Of Frame. When this bit is set, the associated buffer
contains the last data associated with this frame. In the
case of an extra data or overrun error, the buffer may not
contain the actual end of frame data. For a receive header
status the EOF and EOB bits will both be clear.
End Of Buffer. When this bit is set, no more data will be
transferred to the associated data buffer. This may be due
to an end of frame transfer or to reaching the actual end of
the buffer. For a receive header status the EOF and EOB
bits will both be clear.
Address Match:
00 - Individual Address match
01 - Global Address match
10 - Hashed Individual Address
11 - Hashed Multicast Address
RX Error. The RX_Err is set for any receive frame for
which the RX_ERR (MII pin) was activated.
Overrun Error. The receive overrun bit is set on any frame
which could not be completely transferred to system
memory. This could be as a result of insufficient buffer
space, or an excessive bus arbitration time.
Framing Error. This bit is set for any frame not having an
integral number of bytes, and received with a bad CRC
value.
Runt Frame. The Runt bit is set for any receive frame,
including CRC, that is shorter than 64 bytes.
Extra Data. The ExtraData bit indicates that the length of
the incoming frame was equal or greater than the value
programmed in the Max Frame Len register. The receive
frame will be terminated at this maximum length to
conserve system buffer space.
CRC Error. This indicates the frame was received with a
bad CRC.
CRC Included. This bit is set to one when the CRC has
been included in the Receive data buffer. Including or
excluding the CRC is controlled by the BufferCRC bit in
the RXCtl register.
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
9-19
9

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