EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 357

• Manufacturer Part Number: EP9302-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-CQZ

• Program Memory Type: ROMless
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Data Ram Size: 16 bit
• Interface Type: USB, USART, SPI
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 37
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1137

TXCollCnt
RXMissCnt
DS785UM1
31
15
31
15
Address:
Chip Reset:
Soft Reset:
Definition:
Bit Descriptions:
Address:
Chip Reset:
Soft Reset:
30
14
30
14
29
13
29
13
28
12
28
12
0x8001_0070 - Read Only
0x0000_0000
0x0000_0000
Transmit Collision Count Register
RSVD:
TXC:
0x8001_0074 - Read Only
0x0000_0000
0x0000_0000
27
11
27
11
26
10
26
10
Copyright 2007 Cirrus Logic
25
25
9
9
Reserved. Unknown During Read.
Transmit Collision Count. The transmit collision count
records the total number of collisions experienced on the
transmit interface, including late collisions. When the most
significant bit of the count is set, an optional interrupt may
be generated. The register is cleared automatically
following a read and writing to the register will have no
effect.
24
24
8
8
RSVD
RSVD
RMC
TXC
23
23
7
7
22
22
6
6
21
21
1/10/100 Mbps Ethernet LAN Controller
5
5
20
20
4
4
19
19
3
3
EP93xx User’s Guide
18
18
2
2
17
17
1
1
16
16
9-55
0
0
9