EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 227

• Manufacturer Part Number: EP9302-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-CQZ

• Program Memory Type: ROMless
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Data Ram Size: 16 bit
• Interface Type: USB, USART, SPI
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 37
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1137

HClkStrtStop
DS785UM1
31
15
Address: 0x8003_001C
Default: 0x0000_0000
Definition: Horizontal Clock Active Start/Stop register
Bit Descriptions:
Note: When horizontal clock gating is required, set the STRT and STOP fields in the
30
14
RSVD
RSVD
HActiveStrtStop register to the STRT and STOP values in HClkStrtStop + 5. This is a
programming requirement that is easily overlooked.
29
13
28
12
RSVD:
STOP:
STRT:
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Reserved - Unknown during read
Stop - Read/Write
The STOP value is the value of the Horizontal down
counter at which the HCLKEN signal becomes inactive
(stops). This indicates the end of the video clock for the
Horizontal frame. Please refer to video signalling timing
diagrams in
internal clock signal. The SPCLK output is enabled by the
logical AND of VCLKEN and HCLKEN.
Start - Read/Write
The STRT value is the value of the Horizontal down
counter at which the HCLKEN signal becomes active
(starts). This indicates the start of the video clock for the
Horizontal frame. Please refer to video signalling timing
diagrams in
internal clock signal. The SPCLK output is enabled by the
logical AND of VCLKEN and HCLKEN.
Raster Engine With Analog/LCD Integrated Timing and Interface
24
8
23
7
Figure 7-9
Figure 7-9
22
6
STOP
STRT
and
and
21
5
Figure
Figure
20
4
7-10. HCLKEN is an
7-10. HCLKEN is an
19
3
EP93xx User’s Guide
18
2
17
1
16
7-45
0
7