EP9302-CQZ Cirrus Logic Inc, EP9302-CQZ Datasheet - Page 636

• Manufacturer Part Number: EP9302-CQZ
• Description: IC ARM9 SOC PROCESSOR 208LQFP
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9302-CQZ

• Program Memory Type: ROMless
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Data Ram Size: 16 bit
• Interface Type: USB, USART, SPI
• Maximum Clock Frequency: 200 MHz
• Number Of Programmable I/os: 37
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9302A-Z
• Controller Family/series: (ARM9)
• No. Of I/o's: 19
• Ram Memory Size: 16MB
• Cpu Speed: 200MHz
• No. Of Timers: 4
• Embedded Interface Type: AC97, I2S, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1132 - KIT DEVELOPMENT EP9302 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1137

18
18-2
Timers
EP93xx User’s Guide
18.1.2.1 Free Running Mode
18.1.2.2 Pre-load Mode
18.1.3 40-bit Timer Operation
18.2 Registers
In free running mode, counters TC1 and TC2 will wrap to 0xFFFF when they reach zero
(underflow), and continue counting down. Counter TC3 will wrap to 0xFFFFFFFF when it
underflows, and continues counting down.
In pre-load (periodic) mode, the value written to the TC1, TC2 or TC3 Load registers is
automatically re-loaded when the counter underflows. This mode can be used to generate a
programmable periodic interrupt.
The time stamp debug timer is a 40-bit up-counter used only for long term debugging (TC4).
Its clock source is the 14.7456 MHz clock, divided by 15 to give a 983.04 kHz reference. The
timer value may be read at any time by reading the lower 32-bit word first and then the high
byte. Dividing the result by 983 yields a timestamp in milliseconds. The debug timer does not
cause an interrupt. The timer is controlled by a single enable bit. When the timer is enabled, it
begins counting from zero and when it is disabled, it is cleared back to zero. When it reaches
its maximum value (0xFF_FFFF_FFFF) it wraps around to zero and continues counting
upwards.
0x8081_000C
0x8081_002C
0x8081_008C
0x8081_0000
0x8081_0004
0x8081_0008
0x8081_0020
0x8081_0024
0x8081_0028
0x8081_0060
0x8081_0064
0x8081_0080
0x8081_0084
0x8081_0088
0x8081_0010
0x8081_0030
0x8081_0040
0x8081_0090
Address
a. “Enable” is a field in the
Timer4Enable
"Timer4ValueLow"
Read Location
"Timer1Control,"
"Timer2Control,"
"Timer3Control"
"Timer1Value,"
"Timer1Load,"
"Timer1Load,"
"Timer2Value"
"Timer3Value"
"Timer3Load"
Copyright 2007 Cirrus Logic
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
a
/
Table 18-1. Timers Register Map
"Timer4ValueHigh"
"Timer4ValueHigh"
Write Location
"Timer1Control,"
"Timer2Control,"
register.
"Timer1Clear,"
"Timer2Clear,"
"Timer1Load,"
Timer4Enable
"Timer3Clear"
"Timer2Load"
"Timer3Load"
"Timer3Load"
Reserved
Reserved
Reserved
Reserved
-
-
-
-
16 bits
16 bits
16 bits
16 bits
32 bits
32 bits
32 bits
8 bits
8 bits
Size
1 bit
1 bit
1 bit
32
9
-
-
-
-
Reset Value
0
0
0
0
0
0
0
0
0
0
0
-
-
-
-
-
-
-
DS785UM1