PIC24F16KA102-I/SS Microchip Technology, PIC24F16KA102-I/SS Datasheet - Page 10

• Manufacturer Part Number: PIC24F16KA102-I/SS
• Description: IC PIC MCU FLASH 16K 28-SSOP
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24F16KA102-I/SS

• Program Memory Type: FLASH
• Program Memory Size: 16KB (5.5K x 24)
• Package / Case: 28-SSOP
• Core Processor: PIC
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 24
• Eeprom Size: 512 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC24F
• Core: PIC
• Data Bus Width: 16 bit
• Data Ram Size: 1.5 KB
• Interface Type: I2C/IrDA/SPI/UART
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM240001
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 9-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA240017 - MODULE PLUG-IN PIC24F16KA102 PIM
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC24FXXKAXXX
TABLE 3-4:
3.6
The procedure for writing code memory is the same as
writing the Configuration registers. The difference is
that the 32 instruction words are programmed one at a
time. To facilitate this operation, working registers,
W0:W5, are used as temporary holding registers for the
data to be programmed. Figure 3-8 illustrates the code
memory writing flow.
Table 3-5 provides the ICSP programming details,
including the serial pattern with the ICSP command
code, which must be transmitted LSB first, using the
PGCx and PGDx pins (see Figure 3-2).
In Step 1 of Table 3-5, the Reset vector is exited; in
Step 2, the NVMCON register is initialized for
programming a full row of code memory, and in Step 3,
the 24-bit starting destination address for programming
is loaded into the TBLPAG register and W7 register.
The upper byte of the starting destination address is
stored in TBLPAG and the lower 16 bits of the
destination address are stored in W7.
To minimize the programming time, a packed
instruction format is used (see Figure 3-7).
DS39919A-page 10
Step 1: Exit the Reset vector.
Step 2: Set the NVMCON to erase the entire program memory.
Step 3: Set the TBLPAG and perform dummy table write to select the erased memory.
Step 4: Initiate the erase cycle.
Step 5: Repeat this step to poll the WR bit (bit 15 of NVMCON) until it is cleared by the hardware.
Command
(Binary)
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0001
0000
Writing Code Memory
SERIAL INSTRUCTION EXECUTION FOR CHIP ERASE
000000
040200
000000
24064A
883B0A
200000
880190
200000
BB0800
000000
000000
A8E761
000000
000000
000000
040200
000000
803B02
883C22
000000
<VISI>
000000
(Hex)
Data
NOP
GOTO
NOP
MOV
MOV
MOV
MOV
MOV
TBLWTL W0, [W0]
NOP
NOP
BSET
NOP
NOP
NOP
GOTO
NOP
MOV
MOV
NOP
Clock out the contents of the VISI register.
NOP
Advance Information
0x200
#0x4064, W10
W10, NVMCON
#<PAGEVAL>, W0
W0, TBLPAG
#0x0000, W0
NVMCON, #WR
0x200
NVMCON, W2
W2, VISI
In Step 4 of Table 3-5, four packed instruction words
are stored in working registers, W0:W5, using the MOV
instruction; the Read Pointer, W6, is initialized.
Figure 3-7 illustrates the contents of W0:W5 holding
the packed instruction word data. In Step 5, eight
TBLWT instructions are used to copy the data from
W0:W5 to the write latches of the code memory. Since
code memory is programmed 32 instruction words at a
time, Steps 3 to 5 are repeated eight times to load all
the write latches (see Step 6).
After the write latches are loaded, initiate programming
by writing to the NVMCON register in Steps 7 and 8. In
Step 9, the internal PC is reset to 200h. This is a
precautionary measure to prevent the PC from
incrementing to unimplemented memory when large
devices are being programmed. Finally, in Step 10,
repeat Steps 3 through 9 until all of the code memory is
programmed.
Description
© 2008 Microchip Technology Inc.