ATMEGA329V-8MU Atmel, ATMEGA329V-8MU Datasheet - Page 128

• Manufacturer Part Number: ATMEGA329V-8MU
• Description: IC AVR MCU 32K 8MHZ 64-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA329V-8MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, USART, USI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.9.5
128
ATmega329/3290/649/6490
Phase and Frequency Correct PWM Mode
Note that when using fixed TOP values, the unused bits are masked to zero when any of the
OCR1x Registers are written. As the third period shown in
TOP actively while the Timer/Counter is running in the phase correct mode can result in an
unsymmetrical output. The reason for this can be found in the time of update of the OCR1x Reg-
ister. Since the OCR1x update occurs at TOP, the PWM period starts and ends at TOP. This
implies that the length of the falling slope is determined by the previous TOP value, while the
length of the rising slope is determined by the new TOP value. When these two values differ the
two slopes of the period will differ in length. The difference in length gives the unsymmetrical
result on the output.
It is recommended to use the phase and frequency correct mode instead of the phase correct
mode when changing the TOP value while the Timer/Counter is running. When using a static
TOP value there are practically no differences between the two modes of operation.
In phase correct PWM mode, the compare units allow generation of PWM waveforms on the
OC1x pins. Setting the COM1x1:0 bits to two will produce a non-inverted PWM and an inverted
PWM output can be generated by setting the COM1x1:0 to three (See
The actual OC1x value will only be visible on the port pin if the data direction for the port pin is
set as output (DDR_OC1x). The PWM waveform is generated by setting (or clearing) the OC1x
Register at the compare match between OCR1x and TCNT1 when the counter increments, and
clearing (or setting) the OC1x Register at compare match between OCR1x and TCNT1 when
the counter decrements. The PWM frequency for the output when using phase correct PWM can
be calculated by the following equation:
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR1x Register represent special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCR1x is set equal to BOTTOM the
output will be continuously low and if set equal to TOP the output will be continuously high for
non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. If
OCR1A is used to define the TOP value (WGM13:0 = 11) and COM1A1:0 = 1, the OC1A output
will toggle with a 50% duty cycle.
The phase and frequency correct Pulse Width Modulation, or phase and frequency correct PWM
mode (WGM13:0 = 8 or 9) provides a high resolution phase and frequency correct PWM wave-
form generation option. The phase and frequency correct PWM mode is, like the phase correct
PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM
(0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output mode, the
Output Compare (OC1x) is cleared on the compare match between TCNT1 and OCR1x while
counting up, and set on the compare match while counting down. In inverting Compare Output
mode, the operation is inverted. The dual-slope operation gives a lower maximum operation fre-
quency compared to the single-slope operation. However, due to the symmetric feature of the
dual-slope PWM modes, these modes are preferred for motor control applications.
The main difference between the phase correct, and the phase and frequency correct PWM
mode is the time the OCR1x Register is updated by the OCR1x Buffer Register, (see
8
and
Figure
16-9).
f
OCnxPCPWM
=
--------------------------- -
2 N TOP
⋅
f
clk_I/O
⋅
Figure 16-8
illustrates, changing the
Table 1 on page
2552K–AVR–04/11
Figure 16-
133).