ATMEGA329V-8MU Atmel, ATMEGA329V-8MU Datasheet - Page 78

• Manufacturer Part Number: ATMEGA329V-8MU
• Description: IC AVR MCU 32K 8MHZ 64-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA329V-8MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, USART, USI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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ATmega329/3290/649/6490
• TDO, ADC6 – Port F, Bit 6
ADC6, Analog to Digital Converter, Channel 6
TDO, JTAG Test Data Out: Serial output data from Instruction Register or Data Register. When
the JTAG interface is enabled, this pin can not be used as an I/O pin. In TAP states that shift out
data, the TDO pin drives actively. In other states the pin is pulled high.
• TMS, ADC5 – Port F, Bit 5
ADC5, Analog to Digital Converter, Channel 5
TMS, JTAG Test mode Select: This pin is used for navigating through the TAP-controller state
machine. When the JTAG interface is enabled, this pin can not be used as an I/O pin.
• TCK, ADC4 – Port F, Bit 4
ADC4, Analog to Digital Converter, Channel 4
TCK, JTAG Test Clock: JTAG operation is synchronous to TCK. When the JTAG interface is
enabled, this pin can not be used as an I/O pin.
• ADC3 - ADC0 – Port F, Bit 3:0
Analog to Digital Converter, Channel 3-0.
Table 13-19. Overriding Signals for Alternate Functions in PF7:PF4
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
DIEOV
DI
AIO
PF7/ADC7/TDI
JTAGEN
1
JTAGEN
0
0
0
–
JTAGEN
0
–
TDI
ADC7 INPUT
PF6/ADC6/TDO
JTAGEN
1
JTAGEN
SHIFT_IR +
SHIFT_DR
JTAGEN
TDO
–
JTAGEN
0
–
ADC6 INPUT
.
.
.
PF5/ADC5/TMS
JTAGEN
1
JTAGEN
0
0
0
–
JTAGEN
0
–
TMS
ADC5 INPUT
PF4/ADC4/TCK
JTAGEN
1
JTAGEN
0
0
0
–
JTAGEN
0
–
TCK
ADC4 INPUT
2552K–AVR–04/11