ATMEGA329V-8MU Atmel, ATMEGA329V-8MU Datasheet - Page 241

• Manufacturer Part Number: ATMEGA329V-8MU
• Description: IC AVR MCU 32K 8MHZ 64-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA329V-8MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATMEGA32x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SPI, USART, USI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

23.4.3
2552K–AVR–04/11
LCDFRR – LCD Frame Rate Register
Table 23-3.
Note:
• Bit 7 – Reserved Bit
This bit is reserved bit in the ATmega329/3290/649/6490 and will always read as zero.
• Bits 6:4 – LCDPS2:0: LCD Prescaler Select
The LCDPS2:0 bits selects tap point from a prescaler. The prescaled output can be further
divided by setting the clock divide bits (LCDCD2:0). The different selections are shown in
23-4. Together they determine the prescaled LCD clock (clk
module.
Table 23-4.
• Bit 3 – Reserved Bit
This bit is reserved bit in the ATmega329/3290/649/6490 and will always read as zero.
• Bits 2:0 – LCDCD2:0: LCD Clock Divide 2, 1, and 0
The LCDCD2:0 bits determine division ratio in the clock divider. The various selections are
shown in
Bit
(0xE6)
Read/Write
Initial Value
LCDPM3
LCDPS2
1
1
1
0
0
0
0
1
1
1
1
1. LCDPM3 is reserved and will always read as zero in ATmega329/649.
Table
LCDPM2
LCDPS1
LCD Port Mask (Values in bold are only available in ATmega3290/6490)
LCD Prescaler Select
R
23-5. This Clock Divider gives extra flexibility in frame rate selection.
1
1
1
7
–
0
0
0
1
1
0
0
1
1
LCDPS2
R/W
LCDPM1
LCDPS0
6
0
0
1
1
0
1
0
1
0
1
0
1
LCDPS1
R/W
5
0
LCDPM0
Output from
clk
clk
clk
clk
clk
clk
Prescaler
clk
clk
clk
1
0
1
LCD
LCD
LCD
LCDPS0
LCD
LCD
LCD
LCD
LCD
R/W
LCD
4
0
/1024
/2048
/4096
/128
/256
/512
/16
/64
/N
ATmega329/3290/649/6490
I/O Port in Use as
Segment Driver
R
3
–
0
Duty = 1/4, and Frame Rate = 64 Hz
SEG0:36
SEG0:38
SEG0:39
Frequency when LCDCD2:0 = 0,
Applied Prescaled LCD Clock
LCDCD2
R/W
2
0
LCD_PS
LCDCD1
130kHz
260kHz
520kHz
R/W
8.1kHz
33kHz
66kHz
1MHz
2MHz
1
0
), which is clocking the LCD
Maximum Number
of Segments
LCDCD0
R/W
0
0
37
39
40
LCDFRR
Table
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