COP8SGR728M7/NOPB National Semiconductor, COP8SGR728M7/NOPB Datasheet - Page 21

• Manufacturer Part Number: COP8SGR728M7/NOPB
• Description: MCU 8BIT CMOS ROM OTP 28-SOIC
• Manufacturer: National Semiconductor
• Series: COP8™ 8SGr

Specifications of COP8SGR728M7/NOPB

• Core Processor: COP8
• Core Size: 8-Bit
• Speed: 15MHz
• Connectivity: Microwire/Plus (SPI), UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SOIC
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 15 MHz
• Data Ram Size: 512 B
• Number Of Programmable I/os: 40
• Number Of Timers: 3
• Height: 2.34 mm
• Interface Type: USART
• Length: 17.91 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 7.49 mm
• For Use With: COP8SG-EPU - BOARD PROTOTYPE/TARGET COP8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: COP8SGR728M7

5.0 Functional Description
For operation at lower than maximum R/C oscillator frequency.
For operation at maximum R/C oscillator frequency.
5.11 CONTROL REGISTERS
CNTRL Register (Address X'00EE)
The Timer1 (T1) and MICROWIRE/PLUS control register
contains the following bits:
Bit 7
T1C3
T1C3
T1C2
T1C1
T1C0
MSEL
IEDG
SL1 & SL0 Select the MICROWIRE/PLUS clock divide
T1C2
FIGURE 13. External Oscillator
Timer T1 mode control bit
Timer T1 mode control bit
Timer T1 mode control bit
Timer T1 Start/Stop control in timer
modes 1 and 2, T1 Underflow Interrupt
Pending Flag in timer mode 3
Selects G5 and G4 as MICROWIRE/PLUS
signals SK and SO respectively
External interrupt edge polarity select
(0 = Rising edge, 1 = Falling edge)
by (00 = 2, 01 = 4, 1x = 8)
FIGURE 14. R/C Oscillator
T1C1
T1C0
MSEL
10131721
10131719
IEDG
10131720
SL1
(Continued)
SL0
Bit 0
21
PSW Register (Address X'00EF)
The PSW register contains the following select bits:
The Half-Carry flag is also affected by all the instructions that
affect the Carry flag. The SC (Set Carry) and R/C (Reset
Carry) instructions will respectively set or clear both the carry
flags. In addition to the SC and R/C instructions, ADC,
SUBC, RRC and RLC instructions affect the Carry and Half
Carry flags.
ICNTRL Register (Address X'00E8)
The ICNTRL register contains the following bits:
T2CNTRL Register (Address X'00C6)
The T2CNTRL control register contains the following bits:
Bit 7
T2C3
Bit 7
Bit 7
HC
C
T1PNDA Timer T1 Interrupt Pending Flag (Autoreload RA
T1ENA
EXPND
BUSY
EXEN
GIE
Reserved This bit is reserved and must be zero
LPEN
T0PND
T0EN
µWPND
µWEN
T1PNDB Timer T1 Interrupt Pending Flag for T1B cap-
T1ENB
T2C3
T2C2
T2C1
T2C0
T2PNDA Timer T2 Interrupt Pending Flag (Autoreload
T2ENA
T2PNDB Timer T2 Interrupt Pending Flag for T2B cap-
T2ENB
HC
Reserved
T2C2
C
LPEN
T1PNDA T1ENA
Half Carry Flag
Carry Flag
in mode 1, T1 Underflow in Mode 2, T1A capture
edge in mode 3)
Timer T1 Interrupt Enable for Timer Underflow
or T1A Input capture edge
External interrupt pending
MICROWIRE/PLUS busy shifting flag
Enable external interrupt
Global interrupt enable (enables interrupts)
L
Wakeup/Interrupt)
Timer T0 Interrupt pending
Timer T0 Interrupt Enable (Bit 12 toggle)
MICROWIRE/PLUS interrupt pending
Enable MICROWIRE/PLUS interrupt
ture edge
Timer T1 Interrupt Enable for T1B Input capture
edge
Timer T2 mode control bit
Timer T2 mode control bit
Timer T2 mode control bit
Timer
modes 1 and 2, T2 Underflow Interrupt Pend-
ing Flag in timer mode 3
RA in mode 1, T2 Underflow in mode 2, T2A
capture edge in mode 3)
Timer T2 Interrupt Enable for Timer Underflow
or T2A Input capture edge
ture edge
Timer T2 Interrupt Enable for Timer Underflow
or T2B Input capture edge
T2C1
T0PND T0EN µWPND µWEN
Port
T2
T2C0
Interrupt
Start/Stop
T2PNDA
EXPND
Enable
T2ENA
BUSY EXEN
control
T1PNDB
T2PNDB
www.national.com
(Multi-Input
in
T1ENB
T2ENB
Bit 0
Bit 0
timer
GIE
Bit 0