COP8SGR728M7/NOPB National Semiconductor, COP8SGR728M7/NOPB Datasheet - Page 23

• Manufacturer Part Number: COP8SGR728M7/NOPB
• Description: MCU 8BIT CMOS ROM OTP 28-SOIC
• Manufacturer: National Semiconductor
• Series: COP8™ 8SGr

Specifications of COP8SGR728M7/NOPB

• Core Processor: COP8
• Core Size: 8-Bit
• Speed: 15MHz
• Connectivity: Microwire/Plus (SPI), UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SOIC
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 15 MHz
• Data Ram Size: 512 B
• Number Of Programmable I/os: 40
• Number Of Timers: 3
• Height: 2.34 mm
• Interface Type: USART
• Length: 17.91 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 7.49 mm
• For Use With: COP8SG-EPU - BOARD PROTOTYPE/TARGET COP8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: COP8SGR728M7

6.0 Timers
In this mode the input pin TxB can be used as an indepen-
dent positive edge sensitive interrupt input if the TxENB
control flag is set. The occurrence of a positive edge on the
TxB input pin is latched into the TxPNDB flag.
Figure 16 shows a block diagram of the timer in External
Event Counter mode.
Note: The PWM output is not available in this mode since the TxA pin is being
6.2.3 Mode 3. Input Capture Mode
Each device can precisely measure external frequencies or
time external events by placing the timer block, Tx, in the
input capture mode. In this mode, the reload registers serve
as independent capture registers, capturing the contents of
the timer when an external event occurs (transition on the
timer input pin). The capture registers can be read while
maintaining count, a feature that lets the user measure
elapsed time and time between events. By saving the timer
FIGURE 16. Timer in External Event Counter Mode
used as the counter input clock.
FIGURE 15. Timer in PWM Mode
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value when the external event occurs, the time of the exter-
nal event is recorded. Most microcontrollers have a latency
time because they cannot determine the timer value when
the external event occurs. The capture register eliminates
the latency time, thereby allowing the applications program
to retrieve the timer value stored in the capture register.
In this mode, the timer Tx is constantly running at the fixed t
rate. The two registers, RxA and RxB, act as capture regis-
ters. Each register acts in conjunction with a pin. The register
RxA acts in conjunction with the TxA pin and the register RxB
acts in conjunction with the TxB pin.
The timer value gets copied over into the register when a
trigger event occurs on its corresponding pin. Control bits,
TxC3, TxC2 and TxC1, allow the trigger events to be speci-
fied either as a positive or a negative edge. The trigger
condition for each input pin can be specified independently.
The trigger conditions can also be programmed to generate
interrupts. The occurrence of the specified trigger condition
on the TxA and TxB pins will be respectively latched into the
pending flags, TxPNDA and TxPNDB. The control flag Tx-
ENA allows the interrupt on TxA to be either enabled or
disabled. Setting the TxENA flag enables interrupts to be
generated when the selected trigger condition occurs on the
TxA pin. Similarly, the flag TxENB controls the interrupts
from the TxB pin.
Underflows from the timer can also be programmed to gen-
erate interrupts. Underflows are latched into the timer TxC0
pending flag (the TxC0 control bit serves as the timer under-
flow interrupt pending flag in the Input Capture mode). Con-
sequently, the TxC0 control bit should be reset when enter-
ing the Input Capture mode. The timer underflow interrupt is
enabled with the TxENA control flag. When a TxA interrupt
occurs in the Input Capture mode, the user must check both
the TxPNDA and TxC0 pending flags in order to determine
whether a TxA input capture or a timer underflow (or both)
caused the interrupt.
Figure 17 shows a block diagram of the timer T1 in Input
Capture mode. Timer T2 and T3 are identical to T1.
FIGURE 17. Timer in Input Capture Mode
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