COP8SGR728M7/NOPB National Semiconductor, COP8SGR728M7/NOPB Datasheet - Page 34

• Manufacturer Part Number: COP8SGR728M7/NOPB
• Description: MCU 8BIT CMOS ROM OTP 28-SOIC
• Manufacturer: National Semiconductor
• Series: COP8™ 8SGr

Specifications of COP8SGR728M7/NOPB

• Core Processor: COP8
• Core Size: 8-Bit
• Speed: 15MHz
• Connectivity: Microwire/Plus (SPI), UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SOIC
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 15 MHz
• Data Ram Size: 512 B
• Number Of Programmable I/os: 40
• Number Of Timers: 3
• Height: 2.34 mm
• Interface Type: USART
• Length: 17.91 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 7.49 mm
• For Use With: COP8SG-EPU - BOARD PROTOTYPE/TARGET COP8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: COP8SGR728M7

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9.0 Comparators
A Comparator Select Register (CMPSL) is used to enable
the comparators, read the outputs of the comparators inter-
nally, and enable the outputs of the comparators to the pins.
Two control bits (enable and output enable) and one result
bit are associated with each comparator. The comparator
result bits (CMP1RD and CMP2RD) are read only bits which
The CMPSL register contains the following bits:
Reserved These bits are reserved and must be zero
CMP20E Selects pin I6 as comparator 2 output provided
CMP2RD Comparator 2 result (this is a read only bit, which
CMP2EN Enable comparator 2
CMP10E Selects pin I3 as comparator 1 output provided
CMP1RD Comparator 1 result (this is a read only bit, which
CMP1EN Enable comparator 1
Note that the two unused bits of CMPSL may be used as
software flags.
Note: If the user attempts to use the comparator output
immediately after enabling the comparator, an incorrect
value may be read. At least one instruction cycle should pass
between these operations. The use of a direct addressing
mode instruction for either of these two operations will guar-
antee this delay in the software.
F1 Comparator1 negative input
Reserved
Bit 7
that CMP2EN is set to enable the comparator
will read as 0 if the comparator is not enabled)
that CMPIEN is set to enable the comparator
will read as 0 if the comparator is not enabled)
CMP20E
(Continued)
CMP2RD
FIGURE 25. Interrupt Block Diagram
CMP2EN
34
CMP10E
will read as zero if the associated comparator is not enabled.
The Comparator Select Register is cleared with reset, result-
ing in the comparators being disabled. The comparators
should also be disabled before entering either the HALT or
IDLE modes in order to save power. The configuration of the
CMPSL register is as follows:
CMPSL REGISTER (ADDRESS X’00B7)
Note: For compatibility with existing code and with existing Mask ROMMed
10.0 Interrupts
10.1 INTRODUCTION
Each device supports thirteen vectored interrupts. Interrupt
sources include Timer 0, Timer 1, Timer 2, Timer 3, Port L
Wakeup, Software Trap, MICROWIRE/PLUS, and External
Input.
All interrupts force a branch to location 00FF Hex in program
memory. The VIS instruction may be used to vector to the
appropriate service routine from location 00FF Hex.
The Software trap has the highest priority while the default
VIS has the lowest priority.
Each of the 13 maskable inputs has a fixed arbitration rank-
ing and vector.
Figure 25 shows the Interrupt Block Diagram.
devices the bits of the CMPSL register will take precedence over the
associated Port F configuration and data output bits.
CMP1RD
CMP1EN
10131728
Reserved
Bit 0