COP8SGR728M7/NOPB National Semiconductor, COP8SGR728M7/NOPB Datasheet - Page 46

• Manufacturer Part Number: COP8SGR728M7/NOPB
• Description: MCU 8BIT CMOS ROM OTP 28-SOIC
• Manufacturer: National Semiconductor
• Series: COP8™ 8SGr

Specifications of COP8SGR728M7/NOPB

• Core Processor: COP8
• Core Size: 8-Bit
• Speed: 15MHz
• Connectivity: Microwire/Plus (SPI), UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 28-SOIC
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 15 MHz
• Data Ram Size: 512 B
• Number Of Programmable I/os: 40
• Number Of Timers: 3
• Height: 2.34 mm
• Interface Type: USART
• Length: 17.91 mm
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 7.49 mm
• For Use With: COP8SG-EPU - BOARD PROTOTYPE/TARGET COP8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: COP8SGR728M7

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13.0 Memory Map
All RAM, ports and registers (except A and PC) are mapped
into data memory address space.
0000 to 006F
0070 to 007F
xx80 to xx93
xx94
xx95
xx96
xx97 to xxAF
xxB0
xxB1
xxB2
xxB3
xxB4
xxB5
xxB6
xxB7
xxB8
xxB9
xxBA
xxBB
xxBC
xxBD
xxBE
xxBF
xxC0
xxC1
xxC2
xxC3
xxC4
xxC5
xxC6
xxC7
xxC8
S/ADD REG
Address
On-Chip RAM bytes (112 bytes)
Unused RAM Address Space (Reads As
All Ones)
Unused RAM Address Space (Reads
Undefined Data)
Port F data register, PORTFD
Port F configuration register, PORTFC
Port F input pins (read only), PORTFP
Unused address space (Reads Undefined
Data)
Timer T3 Lower Byte
Timer T3 Upper Byte
Timer T3 Autoload Register T3RA Lower
Byte
Timer T3 Autoload Register T3RA Upper
Byte
Timer T3 Autoload Register T3RB Lower
Byte
Timer T3 Autoload Register T3RB Upper
Byte
Timer T3 Control Register
Comparator Select Register (Reg:CMPSL)
UART Transmit Buffer (Reg:TBUF)
UART Receive Buffer (Reg:RBUF)
UART Control and Status Register
(Reg:ENU)
UART Receive Control and Status
Register (Reg:ENUR)
UART Interrupt and Clock Source Register
(Reg:ENUI)
UART Baud Register (Reg:BAUD)
UART Prescale Select Register (Reg:PSR)
Reserved for UART
Timer T2 Lower Byte
Timer T2 Upper Byte
Timer T2 Autoload Register T2RA Lower
Byte
Timer T2 Autoload Register T2RA Upper
Byte
Timer T2 Autoload Register T2RB Lower
Byte
Timer T2 Autoload Register T2RB Upper
Byte
Timer T2 Control Register
WATCHDOG Service Register
(Reg:WDSVR)
MIWU Edge Select Register
(Reg:WKEDG)
Contents
46
Note: Reading memory locations 0070H–007FH (Segment 0) will return all
xxC9
xxCA
xxCB to xxCF Reserved
xxD0
xxD1
xxD2
xxD3
xxD4
xxD5
xxD6
xxD7
xxD8
xxD9
xxDA
xxDB
xxDC
xxDD to xxDF Reserved for Port D
xxE0 to xxE5
xxE6
xxE7
xxE8
xxE9
xxEA
xxEB
xxEC
xxED
xxEE
xxEF
xxF0 to FB
xxFC
xxFD
xxFE
xxFF
0100–017F
0200–027F
0300–037F
S/ADD REG
Address
ones. Reading unused memory locations 0080H–0093H (Segment 0)
will return undefined data. Reading memory locations from other Seg-
ments (i.e., Segment 4, Segment 5, … etc.) will return undefined data.
MIWU Enable Register (Reg:WKEN)
MIWU Pending Register (Reg:WKPND)
Port L Data Register
Port L Configuration Register
Port L Input Pins (Read Only)
Reserved for Port L
Port G Data Register
Port G Configuration Register
Port G Input Pins (Read Only)
Port I Input Pins (Read Only) (Actually
reads Port F input pins)
Port C Data Register
Port C Configuration Register
Port C Input Pins (Read Only)
Reserved for Port C
Port D
Reserved for EE Control Registers
Timer T1 Autoload Register T1RB Lower
Byte
Timer T1 Autoload Register T1RB Upper
Byte
ICNTRL Register
MICROWIRE/PLUS Shift Register
Timer T1 Lower Byte
Timer T1 Upper Byte
Timer T1 Autoload Register T1RA Lower
Byte
Timer T1 Autoload Register T1RA Upper
Byte
CNTRL Control Register
PSW Register
On-Chip RAM Mapped as Registers
X Register
SP Register
B Register
S Register
On-Chip 128 RAM Bytes
On-Chip 128 RAM Bytes (Reads as
undefined data on COP8SGE)
On-Chip 128 RAM Bytes (Reads as
undefined data on COP8SGE)
Contents