MCF5471ZP200 Freescale Semiconductor, MCF5471ZP200 Datasheet - Page 11

• Manufacturer Part Number: MCF5471ZP200
• Description: IC MPU 32BIT COLDF 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF547xr

Specifications of MCF5471ZP200

• Core Processor: Coldfire V4E
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 99
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.43 V ~ 1.58 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 388-BGA
• Family Name: MCF5xxx
• Device Core: ColdFire V4e
• Device Core Size: 32b
• Frequency (max): 200MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5/3.3V
• Operating Supply Voltage (max): 1.58/3.6V
• Operating Supply Voltage (min): 1.43/3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• For Use With: M5475EVBGHS - KIT DEV GHS FOR M5475EVBM5474GFE - MODULE M5474 FIRE ENGINEM5474LITEKIT - KIT DEV FOR MCF547X
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Not Compliant

6
The specifications in
Table 8
Figure 9
Freescale Semiconductor
25.0
1
2
25.0
AD[12:8]
25
CLKIN (MHz)
All other values of AD[12:8] are reserved.
DDR memories typically have a minimum speed of 83 MHz. Some vendors specifiy down to 75 MHz. Check with the
memory component specifications to verify.
shows the supported PLL encodings.
00011
00101
01111
correlates CLKIN, internal bus, and core clock frequencies for the 1x–4x multipliers.
33.33
CLKIN
PLL Timing Specifications
50
66.66
1
70
2x
4x
Table 7
Num
Clock
Ratio
C1
C2
C3
C4
CLKIN
1:2
1:2
1:4
30
Cycle time
Rise time (20% of Vdd to 80% of vdd)
Fall time (80% of Vdd to 20% of Vdd)
Duty cycle (at 50% of Vdd)
are for the CLKIN pin.
50
Internal Clock (MHz)
CLKIN—PCI and FlexBus
50.0
Figure 9. CLKIN, Internal Bus, and Core Clock Ratios
Frequency Range (MHz)
Internal Clock
70
Table 8. MCF547x Divide Ratio Encodings
41.67–66.66
25.0–44.42
Characteristic
25.0–33.3
MCF547x ColdFire
Figure 8. Input Clock Timing Diagram
90
Table 7. Clock Timing Specifications
100.0
110
C4
133.33
130
133.33
C1
2x
2x
C4
®
60
Microprocessor, Rev. 4
Internal XLB, SDRAM Bus,
and PSTCLK Frequency
80
Range (MHz)
83.33–133.33
50.0–88.83
100–133.33
100.0
15.0
C3
Min
100 120 140 160
40
—
—
2
Core Clock (MHz)
C2
Max
40
60
2
2
Core Clock
180 200 220
Core Frequency Range
Units
PLL Timing Specifications
ns
ns
ns
%
200.0
166.66–266.66
100.0–177.66
200–266.66
(MHz)
240 260
266.66
266.66
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