MCF5471ZP200 Freescale Semiconductor, MCF5471ZP200 Datasheet - Page 28

• Manufacturer Part Number: MCF5471ZP200
• Description: IC MPU 32BIT COLDF 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF547xr

Specifications of MCF5471ZP200

• Core Processor: Coldfire V4E
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 99
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.43 V ~ 1.58 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 388-BGA
• Family Name: MCF5xxx
• Device Core: ColdFire V4e
• Device Core Size: 32b
• Frequency (max): 200MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.5/3.3V
• Operating Supply Voltage (max): 1.58/3.6V
• Operating Supply Voltage (min): 1.43/3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 388
• Package Type: BGA
• For Use With: M5475EVBGHS - KIT DEV GHS FOR M5475EVBM5474GFE - MODULE M5474 FIRE ENGINEM5474LITEKIT - KIT DEV FOR MCF547X
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Not Compliant

JTAG and Boundary Scan Timing
Table 23
Figure 28
Figure 29
28
lists specifications for the debug AC timing parameters shown in
shows real-time trace timing for the values in
shows BDM serial port AC timing for the values in
DSCLK
DSO
DSI
PSTDDATA[7:0]
1
DSCLK and DSI are synchronized internally. D4 is measured from the
synchronized DSCLK input relative to the rising edge of CLKOUT.
D3
Num
D4
D1
D2
D3
D5
PSTCLK
1
PSTDDATA to PSTCLK setup
PSTCLK to PSTDDATA hold
DSI-to-DSCLK setup
DSCLK-to-DSO hold
DSCLK cycle time
Table 23. Debug AC Timing Specifications
MCF547x ColdFire
Figure 28. Real-Time Trace AC Timing
Figure 29. BDM Serial Port AC Timing
Characteristic
Current
Past
Table
D4
®
D1
D5
Microprocessor, Rev. 4
Table
23.
23.
Min
4.5
4.5
1
4
5
66 MHz
Figure
D2
Max
—
—
—
—
—
29.
PSTCLKs
PSTCLKs
PSTCLKs
Units
ns
ns
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