MCF5471ZP200 Freescale Semiconductor, MCF5471ZP200 Datasheet - Page 32

IC MPU 32BIT COLDF 388-PBGA

MCF5471ZP200

Manufacturer Part Number
MCF5471ZP200
Description
IC MPU 32BIT COLDF 388-PBGA
Manufacturer
Freescale Semiconductor
Series
MCF547xr
Datasheet

Specifications of MCF5471ZP200

Core Processor
Coldfire V4E
Core Size
32-Bit
Speed
200MHz
Connectivity
EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
Peripherals
DMA, PWM, WDT
Number Of I /o
99
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.43 V ~ 1.58 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
388-BGA
Family Name
MCF5xxx
Device Core
ColdFire V4e
Device Core Size
32b
Frequency (max)
200MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
1.5/3.3V
Operating Supply Voltage (max)
1.58/3.6V
Operating Supply Voltage (min)
1.43/3V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
388
Package Type
BGA
For Use With
M5475EVBGHS - KIT DEV GHS FOR M5475EVBM5474GFE - MODULE M5474 FIRE ENGINEM5474LITEKIT - KIT DEV FOR MCF547X
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MCF5471ZP200
Manufacturer:
Freescale
Quantity:
92
Part Number:
MCF5471ZP200
Manufacturer:
MOTOLOLA
Quantity:
490
Revision History
18
32
Revision
Number
2.2
2.3
2.4
Revision History
3
4
December 14, 2005
February 20, 2007
December 4, 2007
August 29, 2005
August 30, 2005
Date
MCF547x ColdFire
Table
Table
Table
Table
Table
Table
Added
Figure
Figure
or PLL VDD by more than 0.4V...” to “IVDD should not exceed EVDD or SD
VDD by more than 0.4V...”
Table
Table
Table
current.
Table
Added features list, pinout drawing, block diagram, and case outline.
7: Changed C1 maximum spec from 33.3 ns to 40 ns.
22: Changed J11 maximum from 15 ns to 20 ns.
10: Changed FB1 maximum from 33.33 ns to 40 ns.
14: Changed FB1 maximum from 33.33 ns to 40 ns.
4: Updated DC electrical specifications, V
6: Changed FlexBus output load from 20pF to 30pF.
3: Updated thermal information for θ
4: Added input leakage current spec.
6: Added footnote regarding pads having balanced source & sink
9: Added RSTI pulse duration spec.
Section 4.3, “General USB Layout
2: Changed resistor value from 10W to 10Ω
3: Changed note 1 in from “IVDD should not exceed EVDD, SD VDD
®
Microprocessor, Rev. 4
Substantive Changes
Guidelines.”
JMA
, θ
IL
JB
and V
, and θ
IH
Freescale Semiconductor
JC
.

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