UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 559

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
(4) UARTAn option control register 0 (UAnOPT0)
The UAnOPT0 register is an 8-bit register used to control SBF transmission/reception in the LIN
communication format and the level of the transmission/reception signals for the UARTAn.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 14H.
(n = 0 to 5)
UAnOPT0
After reset: 14H
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
Caution Do not set the UAnSRT and UAnSTT bits (to 1) during SBF reception
Note
• This bit indicates whether SBF (Sync Brake Field) is received in LIN communication.
• When an SBF reception error occurs, the UAnSRF bit remains 1 and SBF reception
• The UAnSRF bit is a read-only bit.
• This is the SBF reception trigger bit during LIN communication, and is always 0
• For SBF reception, set the UAnSRT bit (to 1) to enable SBF reception.
• Set the UAnSRT bit after setting the UAnPWR bit and UAnRXE bit to 1.
• This is the SBF transmission trigger bit during LIN communication, and is always 0
• Setting this bit to 1 triggers SBF transmission.
• Set the UAnSTT bit after setting the UAnPWR bit and UAnTXE bit to 1.
UAnSRF
UAnSRT
UAnSTT
UAnSRF
is started again.
when read.
when read.
<7>
0
1
0
1
0
1
μ
PD70F3792, 70F3793 only
The UAnCTL0.UAnPWR bit or the UAnCTL0.UAnRXE bit is set to 0,
or SBF reception ends normally.
During SBF reception
SBF reception trigger
SBF transmission trigger
UAnSRT UAnSTT UAnSLS2 UAnSLS1 UAnSLS0 UAnTDL UAnRDL
(UAnSRF bit = 1).
R/W
6
Address: UA0OPT0 FFFFFA03H, UA1OPT0 FFFFFA13H,
User’s Manual U18953EJ5V0UD
5
UA2OPT0 FFFFFA23H, UA3OPT0 FFFFFA33H
UA4OPT0 FFFFFA43H
SBF transmission trigger
4
SBF reception trigger
SBF reception flag
−
−
3
Note
, UA5OPT0 FFFFFA53H
2
1
Note
0
,
Note
(1/2)
557