UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 771

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

20.6 Transfer Types
cycle, the transfer destination address is output and data is written from the DMAC to the destination.
between the transfer source and destination in two-cycle DMA transfer, the operation is performed as follows.
same transfer size as the register size. For example, to execute DMA transfer on an 8-bit register, be sure to specify
byte (8-bit) transfer.
Two-cycle transfer is supported as the transfer type.
In two-cycle transfer, data is transferred in two cycles, a read cycle and a write cycle.
In the read cycle, the transfer source address is output and data is read from the source to the DMAC. In the write
An idle cycle of one clock is always inserted between a read cycle and a write cycle. If the data bus width differs
<16-bit data transfer (DADCn.DSn0 bit = 1)>
For DMA transfer executed on an on-chip peripheral I/O register (transfer source/destination), be sure to specify the
Remark
<1> Transfer from 32-bit bus to 16-bit bus
<2> Transfer from 16-/32-bit bus to 8-bit bus
<3> Transfer from 8-bit bus to 16-/32-bit bus
<4> Transfer from 16-bit bus to 32-bit bus
A read cycle (the higher or lower 16-bit data) is generated, followed by a write cycle (16 bits).
A 16-bit read cycle is generated once, and then an 8-bit write cycle is generated twice.
An 8-bit read cycle is generated twice, and then a 16-bit write cycle is generated once.
A 16-bit read cycle is generated once, and then a 16-bit write cycle is generated once.
The bus width of each transfer source and destination is as follows.
• On-chip peripheral I/O: 16 bits
• Internal RAM:
• External memory:
CHAPTER 20 DMA FUNCTION (DMA CONTROLLER)
32 bits
8 bits or 16 bits
User’s Manual U18953EJ5V0UD
769