UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 852

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
<R>
850
Item
LVI
Subclock oscillator
Internal oscillator
PLL
CPU
DMA
Interrupt controller
Timer P (TMP0 to TMP5)
Timer Q (TMQ0)
Timer M (TMM0)
Watch timer(/RTC)
Watchdog timer 2
Serial interface
A/D converter
D/A converter
Real-time output function (RTO)
Key interrupt function (KR)
CRC operation circuit
External bus interface
Port function
CPU register set
Internal RAM
Notes1.
Caution When the CPU is operating on the subclock and main clock oscillation is stopped, a register for
Setting of Subclock Operation Mode
2.
Be sure to stop the PLL (PLLCTL.PLLON bit = 0) before stopping the main clock.
μ
which a wait has been specified must not be accessed. If a wait is generated, it can only be
canceled by a reset (see 3.4.8 (2)).
PD70F3792, 70F3793 only
Note2
CSIB0 to CSIB4
I
UARTA0 to UARTA5
UARTC0
2
C00 to I
Table 23-11. Operating Status in Subclock Operation Mode
2
Note2
C02
Operable
Oscillates
Oscillation enabled
Operable
Operable
Operable
Operable
Operable
Operable
Operable
Operable
Operable
Operable
Operable
Operable
Operable
Operable
Operable
Operable
Operable
Operable
See 2.2 Pin States.
Settable
Settable
CHAPTER 23 STANDBY FUNCTION
When Main Clock Is Oscillating
User’s Manual U18953EJ5V0UD
Operating Status
Stops operation
Stops operation
Operable when f
Operable when the SCKBn input clock is
Stops operation (but UARTA0 is
Stops operation (output held)
Stops operation
the count clock
Operable when f
count clock
Operable when f
the count clock
selected as the count clock (n = 0 to 4)
Stops operation
operable when the ASCKA0 input clock
is selected)
Stops operation
Stops operation
When Main Clock Is Stopped
Note1
R
XT
R
/8 or f
or f
is selected as the
XT
XT
is selected as
is selected as