UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 600

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

598
CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC) (
UC0STR
After reset: 00H
UC0TSF
The UC0TSF bit is always 1 when performing continuous transmission. When
initializing the transmission unit, check that the UC0TSF bit is 0 before performing
initialization. The transmit data is not guaranteed when initialization is performed
while the UC0TSF bit is 1.
• The operation of the UC0PE bit is controlled by the settings of the
• Once the UC0PE bit is set (1), the value is retained until the bit is cleared (0).
• The UC0PE bit can be read and written, but it can only be cleared by writing 0 to it;
UC0OVE
UC0TSF
• Only the first bit of the receive data stop bits is checked, regardless of the value
• Once the UC0FE bit is set (1), the value is retained until the bit is cleared (0).
• The UC0FE bit can be both read and written, but it can only be cleared by
• When an overrun error occurs, the data is discarded without the next receive data
• Once the UC0OVE bit is set (1), the value is retained until the bit is cleared (0).
• The UC0OVE bit can be both read and written, but it can only be cleared by writing
UC0PE
UC0FE
UC0CTL0.UC0PS1 and UC0CTL0.UC0PS0 bits.
it cannot be set by writing 1 to it. When 1 is written to this bit, the previous value is
retained.
of the UC0CTL0.UC0SL bit.
writing 0 to it; it cannot be set by writing 1 to it. When 1 is written to this bit, the
previous value is retained.
being written to the receive buffer.
0 to it; it cannot be set by writing 1 to it. When 1 is written to this bit, the previous
value is retained.
<7>
0
1
0
1
0
1
0
1
The transmit shift register does not have data.
The transmit shift register has data.
(Write to UC0TX register)
• When the UC0PWR bit or the UC0RXE bit has been set to 0.
• When 0 has been written
The received parity bit does not match the specified parity.
R/W
• When the UC0PWR bit or the UC0RXE bit has been set to 0
• When 0 has been written
When no stop bit is detected during reception
• When the UC0PWR bit or the UC0RXE bit has been set to 0.
• When 0 has been written
When receive data has been set to the UC0RX register and the next
receive operation is completed before that receive data has been read
• When the UC0PWR bit or the UC0TXE bit has been set to 0.
• When, following transfer completion, there was no next data transfer
from UC0TX register
6
0
Address: FFFFFAA4H
User’s Manual U18953EJ5V0UD
5
0
4
0
Transfer status flag
Overrun error flag
Framing error flag
Parity error flag
3
0
UC0PE
<2>
PD70F3792, 70F3793)
UC0FE
<1>
UC0OVE
<0>