UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 570

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16.6.4 UART reception
(UAnPWR = 0) or clear both the transmission enable bit and reception enable bit (UAnTXE = 0 and UAnRXE = 0)
beforehand.
of data input to RXDAn is started. If the data is low level half a bit after detection of the falling edge (indicated by
Figure 16-9), it is recognized as a start bit. When the start bit has been recognized, reception is started, and serial
data is sequentially stored in the receive shift register at the specified baud rate. When the stop bit has been received,
the reception complete interrupt request signal (INTUAnR) is generated and, at the same time, the data stored in the
receive shift register is transferred to the receive data register (UAnRX).
On the other hand, even if a parity error (UAnPE = 1) or framing error (UAnFE = 1) occurs, reception continues and
the receive data is transferred to the UAnRX register. No matter which reception error has occurred, the INTUAnR
interrupt is generated after reception is complete.
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First, enable reception by executing the following operations and monitor the RXDAn input to detect the start bit.
• Specify the operating clock by using UARTA control register 1 (UAnCTL1).
• Specify the baud rate by using UARTA control register 2 (UAnCTL2).
• Specify the output logic level by using UARTA option control register 0 (UAnOPT0).
• Specify the communication direction, parity, data character length, and stop bit length by using UARTA control
• Set the power bit and reception enable bit (UAnPWR = 1 and UAnRXE = 1).
To change the communication direction, parity, data character length, and/or stop bit length, clear the power bit
The level input to the RXDAn pin is sampled by using the operating clock. If the falling edge is detected, sampling
If an overrun error occurs (UAnOVE = 1), however, the receive data is not transferred to UAnRX, but is discarded.
register 0 (UAnCTL0).
RXDAn
INTUAnR
UAnRX
CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE A (UARTA)
Start
bit
D0
Figure 16-9. UART Reception
D1
User’s Manual U18953EJ5V0UD
D2
D3
D4
D5
D6
D7
Parity
bit
Stop
bit
in