UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 931

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

31.1.2 Interface signals
The interface signals are described below.
(1) DRST
(2) DCK
(3) DMS
(4) DDI
(5) DDO
(6) EV
This is a reset input signal for the on-chip debug unit. It is a negative-logic signal that asynchronously
initializes the debug control unit.
MINICUBE raises the DRST signal when it detects V
started, and starts the on-chip debug unit of the device.
When the DRST signal goes high, a reset signal is also generated in the CPU.
When starting debugging by starting the integrated debugger, a CPU reset is always generated.
This is a clock input signal. It supplies a 20 MHz or 10 MHz clock from MINICUBE. In the on-chip debug unit,
the DMS and DDI signals are sampled at the rising edge of the DCK signal, and the data DDO is output at its
falling edge.
This is a transfer mode select signal. The transfer status in the debug unit changes depending on the level of
the DMS signal.
This is a data input signal. It is sampled in the on-chip debug unit at the rising edge of DCK.
This is a data output signal. It is output from the on-chip debug unit at the falling edge of the DCK signal.
This signal is used to detect VDD of the target system.
If VDD of the target system cannot be detected, MINICUBE makes its output signals (DRST, DCK, DMS, DDI,
FLMD0, and RESET) high-impedance.
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CHAPTER 31 ON-CHIP DEBUG FUNCTION
User’s Manual U18953EJ5V0UD
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of the target system after the integrated debugger is
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