UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 90

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

88
(1) Setting data to special registers
Set data to the special registers in the following sequence.
<1>
<2>
<3>
<4>
(<5> to <9> Insert NOP instructions (5 instructions).)
<10>
There is no special sequence required to read a special register.
Note When switching to the IDLE mode or the STOP mode (PSC.STP bit = 1), 5 NOP instructions must be
Caution To resume the DMA operation in the status before the DMA operation was disabled after a
Remark n = 0 to 3
[Example] PSC register (setting standby mode)
<1>CLR1 0, DCHCn[r0]
<2>MOV0x02, r10
<3>ST.B r10, PRCMD[r0] ; Write PRCMD register.
<4>ST.B r10, PSC[r0]
<5>NOP
<6>NOP
<7>NOP
<8>NOP
<9>NOP
<10>SET1 0, DCHCn[r0]
(next instruction)
ST.B r11, PSMR[r0]
inserted immediately after switching is performed.
Note
Note
Note
Note
Note
special sequence, the DCHCn register status must be stored before the DMA operation is
disabled.
After the DCHCn register status is stored, the DCHCn.TCn bit must be checked before the
DMA operation is resumed and the following processing must be executed according to the
TCn bit status, because completion of DMA transfer may occur before the DMA operation is
disabled.
• When the TCn bit is 0 (DMA transfer not completed), the contents of the DCHCn register
• When the TCn bit is 1 (DMA transfer completed), DMA transfer completion processing is
Disable DMA operation.
Prepare data to be set to the special register in a general-purpose register.
Write the data prepared in <2> to the PRCMD register.
Write the setting data to the special register (by using the following instructions).
• Store instruction (ST/SST instruction)
• Bit manipulation instruction (SET1/CLR1/NOT1 instruction)
Enable DMA operation if necessary.
stored before the DMA operation was disabled are written to the DCHCn register again.
executed.
; Set PSMR register (setting IDLE1, IDLE2, and STOP modes).
; Disable DMA operation. n = 0 to 3
; Set PSC register.
; Dummy instruction
; Dummy instruction
; Dummy instruction
; Dummy instruction
; Dummy instruction
; Enable DMA operation. n = 0 to 3
CHAPTER 3 CPU FUNCTION
User’s Manual U18953EJ5V0UD
Note