UPD70F3738GF-GAS-AX Renesas Electronics America, UPD70F3738GF-GAS-AX Datasheet - Page 669

• Manufacturer Part Number: UPD70F3738GF-GAS-AX
• Description: MCU 32BIT V850ES/JX3-L 100-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Lr

Specifications of UPD70F3738GF-GAS-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 84
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.2 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

SIBn pin capture
INTCBnR signal
(1) Write 07H to the CBnCTL1 register, and select communication type 1, communication clock (f
(2) Write 00H to the CBnCTL2 register, and set the transfer data length to 8 bits.
(3) Write A3H to the CBnCTL0 register, and select the reception mode, MSB first, and continuous transfer
(4) The CBnSTR.CBnTSF bit is set to 1 by performing a dummy read of the CBnRX register, and the
(5) When the serial clock is input, capture the receive data of the SIBn pin in synchronization with the
(6) When reception is completed, the reception complete interrupt request signal (INTCBnR) is generated,
(7) When the serial clock is input with the CBnCTL0.CBnSCE bit set to 1, continuous reception is started.
(8) To end continuous reception with the current reception, clear the CBnSCE bit to 0.
(9) Read the CBnRX register.
(10) When reception is completed, the INTCBnR signal is generated, and reading receive data from the
(11) Read the CBnRX register.
(12) To disable reception, clear the CBnCTL0.CBnPWR and CBnCTL0.CBnRXE bits to 0 after confirming
Remark
CBnSCE bit
CBnTSF bit
SCKBn pin
SIBn pin
Figure 18-26. Continuous Transfer Mode Operation Timing (Slave Mode, Reception Mode)
timing
external clock (SCKBn), and slave mode.
mode at the same time as enabling the operation of the communication clock (f
device waits for serial clock input.
serial clock.
and reading receive data from the CBnRX register is enabled.
CBnRX register is enabled. If the CBnSCE bit is set to 0 before communication is complete, clear the
CBnTSF bit to 0 to end the receive operation.
that the CBnTSF bit is 0.
n = 0 to 4
(1)
(2)
(3)
(4)
(5)
Bit 7
CHAPTER 18 CLOCKED SERIAL INTERFACE B (CSIB)
Bit 6
Bit 5
Bit 4 Bit 3
User’s Manual U18953EJ5V0UD
Bit 2
Bit 1
(6) (7) (8) (9)
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4 Bit 3
Bit 2
CCLK
).
Bit 1
(10)
Bit 0
(11) (12)
CCLK
) =
667