UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 1312

• Manufacturer Part Number: UPD70F3771GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-H 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Hr

Specifications of UPD70F3771GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CAN, CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(2) Releasing HALT mode by reset
Note
Item
Main clock oscillator (f
Subclock oscillator (f
Internal oscillator (f
PLL
CPU
DMA controller
Interrupt controller
Timer
Real-time counter (RTC)
Watchdog timer (WDT2)
Serial interface
A/D converter
D/A converter
Real-time output function (RTO)
Key interrupt function (KR)
CRC operation circuit
External bus interface
Port function
Internal data
CAN
USB function
The same operation as the normal reset operation is performed.
Note
μ
PD70F3770, 70F3771 only
TAA0 to TAA5
TAB0, TAB1
TMM0 to TMM3
TMT0
CSIF0 to CSIF4
I
UARTC0 to UARTC4
R
2
Setting of HALT Mode
C00 to I
)
XT
X
)
)
2
C02
Table 25-3. Operating Status in HALT Mode
Oscillation enabled
Oscillation enabled
Operable
Stops operation
Operable
Operable
Operable
Operable
Operable when a clock other than f
selected as the count clock
Operable
Operable when f
selected as the count clock
Operable when a clock other than f
selected as the count clock
Operable
Operable
Operable
Operable
Operable
Operable
Operable
Operable (No data input to the CRCIN register because the CPU is stopped)
See CHAPTER 5 BUS CONTROL FUNCTION.
Retains status before HALT mode was set
The CPU registers, statuses, data, and all other internal data such as the contents of
the internal RAM are retained as they were before the HALT mode was set.
Operable
Operable
When Subclock Is Not Used
X
(divided BRG) is
−
Operating Status
XT
XT
is
is
CHAPTER 25 STANDBY FUNCTION
Oscillation enabled
Operable
Operable
Operable
When Subclock Is Used
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