UPD70F3771GF-GAT-AX Renesas Electronics America, UPD70F3771GF-GAT-AX Datasheet - Page 314

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UPD70F3771GF-GAT-AX

Manufacturer Part Number
UPD70F3771GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-H 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Hr
Datasheet

Specifications of UPD70F3771GF-GAT-AX

Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CAN, CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD70F3771GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
V850ES/JG3-H, V850ES/JH3-H
R01UH0042EJ0400 Rev.4.00
Sep 30, 2010
(2) Settings in free-running timer mode (capture function)
[Initial settings]
[Starting counting]
[End condition]
Master timer: TAA1CTL0.TAA1CE = 0 (operation disabled)
Slave timer: TAA0CTL0.TAA0CE = 0 (operation disabled)
[Initial settings of master timer (TAA1)]
[Initial settings of slave timer (TAA0)]
Remark
<1> Set TAA1CTL0.TAA1CE of the master timer to 1.
<2> Start counting.
• Set TAA1CTL0.TAA1CE of the master timer to 0.
• TAA1CTL1.TAA1MD2 to TAA1CTL1.TAA1MD0 = 101 (setting of free-running timer mode)
• TAA1OPT0.TAA1CCS1 and TAA1OPT0.TAA1CCS0 = 11 (setting of capture/compare select bit to “capture”.)
• TAA1CTL1.TAA1CKS2 to TAA1CTL1.TAA1CKS0 (setting of count clock (any))
• TAA1IOC1.TAA1IS3 to TAA1IOC1.TAA1IS0 (specification of valid edge of capture trigger)
• TAA0CTL1.TAA0SYE = 1 (setting of timer-tuned operation)
• TAA0CTL1.TAA0MD2 to TAA0CTL1.TAA0MD0 = 101 (setting of free-running timer mode)
• TAA0OPT0.TAA0CCS1 and TAA0OPT0.TAA0CCS0 = 11 (setting of capture/compare select bit to “capture”.)
• TAA0IOC1.TAA0IS3 to TAA0IOC1.TAA0IS0 (specification of valid edge of capture trigger)
The initial settings of the master timer and slave timer may be performed in any order.
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
Page 314 of 1509

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